per1warmmask

         The PER1WARMMASK register is used by software to mask the assertion of module reset signals for hardware sequenced warm resets. There is a writeable bit for each module reset signal that is asserted by default on a hardware sequenced warm reset. If the bit is 1, the module reset signal is asserted by a hardware sequenced warm reset. If the bit is 0, the module reset signal is not changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. Any module reset signals that are never asserted by a warm reset have reserved bit offsets and are tied to 0 (read as 0, writes are ignored).

All fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD05000`	`0xFFD05048`

Offset: 0x48

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`					`gpio2` `RW 0x1`	`gpio1` `RW 0x1`	`gpio0` `RW 0x1`	`Reserved`						`uart1` `RW 0x1`	`uart0` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`			`i2c4` `RW 0x1`	`i2c3` `RW 0x1`	`i2c2` `RW 0x1`	`i2c1` `RW 0x1`	`i2c0` `RW 0x1`	`Reserved`		`sptimer1` `RW 0x1`	`sptimer0` `RW 0x1`	`l4systimer1` `RW 0x1`	`l4systimer0` `RW 0x1`	`watchdog1` `RW 0x1`	`watchdog0` `RW 0x1`

per1warmmask Fields

Bit	Name	Description	Access	Reset
26	`gpio2`	Masks hardware sequenced warm reset for GPIO2	`RW`	`0x1`
25	`gpio1`	Masks hardware sequenced warm reset for GPIO1	`RW`	`0x1`
24	`gpio0`	Masks hardware sequenced warm reset for GPIO0	`RW`	`0x1`
17	`uart1`	Masks hardware sequenced warm reset for UART1	`RW`	`0x1`
16	`uart0`	Masks hardware sequenced warm reset forUART0	`RW`	`0x1`
12	`i2c4`	Masks hardware sequenced warm reset for I2C4 controller	`RW`	`0x1`
11	`i2c3`	Masks hardware sequenced warm reset for I2C3 controller	`RW`	`0x1`
10	`i2c2`	Masks hardware sequenced warm reset for I2C2 controller	`RW`	`0x1`
9	`i2c1`	Masks hardware sequenced warm reset for 2C1 controller	`RW`	`0x1`
8	`i2c0`	Masks hardware sequenced warm reset for 2C0 controller	`RW`	`0x1`
5	`sptimer1`	Masks hardware sequenced warm reset for SP timer 1 connected to L4	`RW`	`0x1`
4	`sptimer0`	Masks hardware sequenced warm reset for SP timer 0 connected to L4	`RW`	`0x1`
3	`l4systimer1`	Masks hardware sequenced warm reset for l4sys_timer1	`RW`	`0x1`
2	`l4systimer0`	Masks hardware sequenced warm reset for l4sys_timer0	`RW`	`0x1`
1	`watchdog1`	Masks hardware sequenced warm reset for Watchdog 1	`RW`	`0x1`
0	`watchdog0`	Masks hardware sequenced warm reset for Watchdog 0	`RW`	`0x1`