SRS Address Map

Module Instance Base Address End Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x1080827F
Register Offset Width Access Reset Value Description
SRS00 0x0 32 RW 0x00000000 
SRS00 - SDMA System Address / Argument 2
 / 32-bit block count\n
SRS01 0x4 32 RW 0x00000000 
SRS01 - Block Size / Block Count
SRS02 0x8 32 RW 0x00000000 
SRS02 - Argument 1
SRS03 0xC 32 RO 0x00000000 
SRS03 - Command/Transfer Mode
SRS04 0x10 32 RO 0x00000000 
            The SRS04 - SRS07 registers store the response returned by the card.\n
            The mapping of the actual device response and the SRS04 - SRS07 contents depends on the type of response.
            The type of response is determined by the RTS field (Response Type) for all user-defined commands.\n
            The separate cases are the Auto-CMD12 response (called R1b in the SD Memory Specification) and Auto-CMD23 response (called R1 in the SD Memory Specification).
            Auto-CMD12 and Auto-CMD23 responses are handled by the core automatically and goes to the SRS07 register regardless of the RTS value.\n

            SRS04-SRS07 relation to received response field:
            [list]
            [*] Auto-CMD12 resp: Response field R[39:8] - RESP3[31:0]\n
            [*] Auto-CMD23 resp: Response field R[39:8] - RESP3[31:0]\n
            [*] No response: RTS=00b
            [*] 136-bit: RTS=01b, Response field R[127:8] - {RESP3[23:0], RESP2[31:0], RESP1[31:0], RESP0[31:0]}\n
            [*] 48-bit: RTS=10b, Response field R[39:8] - RESP0[31:0]\n
            [*] 48-bit with BUSY: RTS=11b, Response field R[39:8] - RESP0[31:0]\n
            [/list]

            Implementation note: Registers value are undefined after reset, and will be valid after response is received.
SRS05 0x14 32 RO 0x00000000 
            Described in SRS04.
SRS06 0x18 32 RO 0x00000000 
            Described in SRS04.
SRS07 0x1C 32 RO 0x00000000 
            Described in SRS04.
SRS08 0x20 32 RW 0x00000000 
SRS08 - Data Buffer
SRS09 0x24 32 RO 0x00000000 
SRS09 - Present State Register
SRS10 0x28 32 RO 0x00000000 
SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up)
SRS11 0x2C 32 RO 0x00000000 
SRS11 - Host Control 2 (Clock, Timeout, Reset)
SRS12 0x30 32 RO 0x00000000 
SRS12 - Error/Normal Interrupt Status
SRS13 0x34 32 RO 0x00000000 
SRS13 - Error/Normal Status Enable
SRS14 0x38 32 RO 0x00000000 
SRS14 - Error/Normal Signal Enable
SRS15 0x3C 32 RW 0x00000000 
SRS15 - Host Control #2 / Auto CMD Error Status
SRS16 0x40 32 RO 0x1F6AC8B2 
            SRS16 - Capabilities #1
SRS17 0x44 32 RO 0x88000077 
SRS17 - Capabilities #2
SRS18 0x48 32 RO 0x00202020 
SRS18 - Capabilities #3
SRS19 0x4C 32 RO 0x00000020 
            SRS19 - Capabilities #4
SRS20 0x50 32 RO 0x00000000 
            SRS20 - Force Event\n
            Each field of this register is related to the specific error status. Writing 1 to field will set the status error. This function is provided for SW debug purpose.
SRS21 0x54 32 RO 0x00000000 
SRS21 - ADMA Error Status
SRS22 0x58 32 RW 0x00000000 
SRS22  ADMA/SDMA System Address 1
SRS23 0x5C 32 RW 0x00000000 
SRS23 ADMA/SDMA System Address 2
SRS24 0x60 32 RO 0x00040000 
            SRS24 - Preset Value (Default Speed)\n
            SRS24[31:16] - Default Speed if:\n
            SRS15.V18SE=0\n
            SRS10.HSE=0\n

            HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.
SRS25 0x64 32 RO 0x00040002 
            SRS25 - Preset Value (High Speed and SDR12)\n
            SRS25[15:0] - High Speed if:\n
            SRS15.V18SE=0\n
            SRS.HSE=1\n

            SRS25[31:16] - SDR12 if:\n
            SRS15.V18SE=1\n
            SRS15.UMS=000b\n

            HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.
SRS26 0x68 32 RO 0x00010002 
            SRS26 - Preset Value (SDR25 and SDR50)\n
            SRS26[15:0] - SDR25 if:\n
            SRS15.V18SE=1\n
            SRS15.UMS=001b\n

            SRS26[31:16] - SDR50 if:\n
            SRS15.V18SE=1\n
            SRS15.UMS=010b\n

            HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.
SRS27 0x6C 32 RO 0x00020000 
            SRS27 - Preset Value (SDR104 and DDR50)\n
            SRS27[15:0] - SDR104 if:\n
            SRS15.V18SE=1\n
            SRS15.UMS=011b\n

            SRS27[31:16] - DDR50 if:\n
            SRS15.V18SE=1\n
            SRS15.UMS=100b\n

            HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.
SRS30 0x78 32 RW 0x00000000 
            SRS30 ADMA3 ID Address 1
SRS31 0x7C 32 RW 0x00000000 
            SRS30 ADMA3 ID Address 2