SRS03
SRS03 - Command/Transfer Mode
Module Instance | Base Address | Register Address |
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i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000
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0x10808200
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0x1080820C
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Size: 32
Offset: 0xC
Access: RO
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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SRS03 Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:30 |
Reserved_15
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Reserved bitfield added by Magillem |
RO
|
0x0
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29:24 |
CIDX
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CIDX - Command Index\n This field contains a command number (index) of the command to be sent.\n The index can be defined in range 00-63, which means all commands (CMD00-CMD63 and ACMD00-ACMD63) defined in related specifications are supported.\n Writing this filed triggers the actual command transfer. This field is to be written only when Command Inhibit CMD bit is 0 in Present State Register (SRS09.CICMD).\n To check the list of available commands, refer to the appropriate card/device specifications. |
RW
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0x0
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23:22 |
CT
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CT - Command Type\n This field defines specific type of command. [list] [*] Normal Command (0) - used by default when other command types are not intended to be used [*] Suspend Command (01b) - not used [*] Resume Command (10b) - not used [*] Abort Command (11b) - used when the software wants to stop the current data transfer (read or write data transfer). [/list] The read transfer ends by stopping transfer to the internal buffer. The write transfer ends with releasing DAT line to High-Z state. Then, after sending an Abort Command, the software will issue the software reset.\n The Suspend and Resume Mechanism is not supported by the SD Host version 4.00 and later, and the Suspend and Resume Commands will not be used. |
RW
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0x0
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21 |
DPS
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DPS - Data Present Select\n Set to 1 for commands which transfer data (i.e. read or write data using DAT line).\n Set to 0 for all other commands, including: [list] [*] Commands using only CMD line [*] Commands with busy signalized on DAT[0] line (SRS03.RTS=11b) [/list] |
RW
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0x0
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20 |
CICE
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CICE - Command Index Check Enable\n When set to 1, the host checks if the Command Index field in the response is equal to the SRS03.CIDX value.\n When 0, the check is not performed and Command Index field of the response is ignored.\n Recommended settings depends on response type, see following table for details: [list] [*] SRS03.RTS=00: 0 - No Response [*] SRS03.RTS=01: 0 - R2 [*] SRS03.RTS=10: 0 - R3, R4 [*] SRS03.RTS=10: 1 - R1, R5, R6, R7 [*] SRS03.RTS=11: 1 - R1b, R5b [/list] |
RW
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0x0
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19 |
CRCCE
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CRCCE - Command CRC Check Enable\n When set to 1, the host checks if the CRC field of the response is valid.\n When 0, the CRC check is disabled and the CRC field of the response is ignored.\n The CRC check should be disabled for responses which do not contain an actual CRC value (some responses contain all 1s in place of the CRC field), and enabled for all other kinds of responses.\n Recommended settings depends on response type, see following table for details:\n SRS03.RTS=00: 0 - No Response\n SRS03.RTS=01: 1 - R2\n SRS03.RTS=10: 0 - R3, R4\n SRS03.RTS=10: 1 - R1, R5, R6, R7\n SRS03.RTS=11: 1 - R1b, R5b |
RW
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0x0
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18 |
SCF
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SCF - Sub Command Flag\n This bit is added from Version 4.10 to distinguish a main command or sub command.\n When issuing a main command, this bit is set to 0 and when issuing a sub command, this bit is set to 1. Setting of this bit is checked by Sub Command Status in Present State register SRS09.SCMDS). Host Driver manages whether main or sub command.\n Host Controller does not refer to this bit to issue the command. \n |
RW
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0x0
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17:16 |
RTS
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RTS - Response Type Select\n Defines the expected response length.\n 00b - no response\n 01b - 136-bit response\n 10b - 48-bit response\n 11b - 48-bit response with BUSY\n Every command implies one of the response types listed above. To check the response type corresponding to a given command, please refer to the appropriate card/device specifications. |
RW
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0x0
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15:9 |
Reserved_8
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Reserved bitfield added by Magillem |
RO
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0x0
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8 |
RID
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RID - Response Interrupt Disable\n When set to 1, the Command Complete Interrupt (SRS12.CC) will be disabled. The host will ignore the SRS13.CC_SE and behave as the SRS13.CC_SE would be 0.\n When set to 0, the SRS12.CC will be enabled or disabled depend on the SRS13.CC_SE bit only. |
RW
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0x0
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7 |
RECE
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RECE - Response Error Check Enable\n When set 1, the host will look after R1/R5 responses.\n If any error will be detected in the response, the SRS12.ERSP bit is set to 1.\n The software will set this bit only when R1/R5 response is expected.\n The software will set SRS03.RID and RECE bits to 1 when the host checks R1/R5 errors. And both bits will be clear to 0, when the Software Driver will checks R1/R5 errors. On response error, the SRS12.ERSP bit (in Interrupt Status) is set 1. |
RW
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0x0
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6 |
RECT
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RECT - Response Type R1/R5\n Select R1 or R5 response type for the response content checker. Listed below error bits will be evaluated.\n RECT = 0, Response Type - R1 (SD Memory):\n [list] [*] bit 31 OUT_OF_RANGE [*] bit 30 ADDRESS_ERROR [*] bit 29 BLOCK_LEN_ERROR [*] bit 26 WP_VIOLATION [*] bit 25 CARD_IS_LOCKED [*] bit 23 COM_CRC_ERROR [*] bit 21 CARD_ECC_FAILED [*] bit 20 CC_ERROR [*] bit 19 ERRORRECT [/list] RECT = 1, Response Type - R5 (SDIO):\n [list] [*] bit 7 COM_CRC_ERROR [*] bit 3 ERROR [*] bit 1 FUNCTION_NUMBER [*] bit 0 OUT_OF_RANGE [/list] This field is ignored when SRS03.RECE=0. |
RW
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0x0
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5 |
MSBS
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MSBS - Multi/Single Block Select\n Multi-block or single-block data transfer can be selected with this field.\n 0 - Single-block\n 1 - Multi-block\n This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT). When CIDAT=1, all writes to this field are ignored. |
RW
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0x0
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4 |
DTDS
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DTDS - Data Transfer Direction Select\n Selects direction of data transfer for commands with DPS=1. [list] [*] 0 - Write [*] 1 - Read [/list] For commands with SRS03.DPS=0, this field is ignored.\n This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT). When CIDAT=1, all writes to this field are ignored. |
RW
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0x0
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3:2 |
ACE
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ACE - Auto CMD Enable\n The field allows to send one additional command to the card/device when the command is issued.\n [list] [*] 00b - No auto command [*] 01b - Auto CMD12 [*] 10b - Auto CMD23 [*] 11b - Auto CMD Auto Select [/list] If Auto CMD disable (00b) is set, the host does not send any additional command. This setting will be used when auto command is not required or not intended.\n If Auto CMD12 (01b) is set, the host sends CMD12 (Abort) automatically when last block of multi-block transfer is completed.\n If Auto CMD23 (10b) is set, the host sends CMD23 (Set Block Count) automatically before issued transfer data command. An argument of this command can be set in SRS00.\n If Auto CMD Auto Select (11b) is set, the host sends CMD12 or CMD23 according to result of identification process of card. If SRS15.CMD23E == 1 the host sends CMD23 as when as Auto CMD23 is set. If SRS15.CMD23E == 0 the host sends CMD12 as when as Auto CMD12 is set.\n On any error the issued command will not be sent.\n This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT). When SRS09.CIDAT=1, all writes to this field are ignored. |
RW
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0x0
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1 |
BCE
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BCE - Block Count Enable\n When set to 1, active block count register is enabled for the next data transfer. The active register is either SRS01.BCCT or SRS00.SAAR.\n Transfer of each block automatically decrements the counter value. The multi-block transfer ends when the counter reaches 0. So the finite transfer can not be performed with this setting.\n When 0, block counting is disabled, and SRS01.BCCT retains its value.\n The transfer will be infinite in non-DMA and SDMA modes. For ADMA mode the transfer can be infinite or finite. The finite transfer ends on reading the descriptor with END status (so the transfer length is designated by the table of descriptors). In case of infinite transfer, the software will explicitly set ABORT command type to stop transfer.\n This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT). When CIDAT=1, all writes to this field are ignored. |
RW
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0x0
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0 |
DMAE
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DMAE - DMA Enable\n When set to 1, it enables DMA functionality. DMA can be enabled only if it is supported as indicated in the DMA Support in the SRS16.DMAS register. If DMA is not supported (due to host configuration), this bit is ignored.\n This field is hardware-protected by Command Inhibit DAT bit in Present State Register (SRS09.CIDAT).\n When SRS09.CIDAT=1, all writes to this field are ignored.\n Note: The ADMA2 mode uses only the finite transfer mode, i.e. this bit is to be set 1. |
RW
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0x0
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