SRS12 

         SRS12 - Error/Normal Interrupt Status
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x10808230

Size: 32

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_23

RO 0x0

ERSP

RW 0x0

Reserved_22

RO 0x0

EADMA

RW 0x0

EAC

RW 0x0

ECL

RW 0x0

EDEB

RW 0x0

EDCRC

RW 0x0

EDT

RW 0x0

ECI

RW 0x0

ECEB

RW 0x0

ECCRC

RW 0x0

ECT

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EINT

RO 0x0

CQINT

RO 0x0

FXE

RO 0x0

Reserved_9

RO 0x0

CINT

RO 0x0

CR

RW 0x0

CIN

RW 0x0

BRR

RW 0x0

BWR

RW 0x0

DMAINT

RW 0x0

BGE

RW 0x0

TC

RW 0x0

CC

RW 0x0

SRS12 Fields

Bit Name Description Access Reset
31:28 Reserved_23 
Reserved bitfield added by Magillem
 RO 0x0
27 ERSP 
              ERSP - Response Error\n
              Generated on error detection inside R1 or R5 response.\n
              Errors will be checked only if RECE is set 1.
RW 0x0
26 Reserved_22 
Reserved bitfield added by Magillem
 RO 0x0
25 EADMA 
              EADMA - ADMA Error\n
              Generated when an error occurs during ADMA read or write transfer.\n
              To resolve the cause of the error, the state of the ADMA engine at error occurrence is saved in ADMA Error Status register,
              and the address of the descriptor processed at error occurrence is provided in ADMA System Address register.
RW 0x0
24 EAC 
              EAC - Auto CMD Error (SD mode only)\n
              Generated when an error occurs during Auto CMD12/Auto CMD23 command transmission.\n
              It indicates one of the following conditions:\n
              - one of the bits in SRS15 register has changed from 0 to 1,\n
              - Auto CMD12 is not executed due to the previous command error.
RW 0x0
23 ECL 
              ECL - Current Limit Error\n
              This fields carries an error/failure reported on the \textit{pad_cle} input pad of the Host Controller.
              The error/failure generation is located outside of this soft IP.\n\n
              Note: If the external power supply for SD/eMMC device does not monitor and report this type of error, connect the Current Limit Error (\textit{sdphy_dfi_cle} input of the Host Controller core) to 0.
RW 0x0
22 EDEB 
              EDEB - Data End Bit Error (SD mode only)\n
              When set to 1, indicates detecting 0 at the end bit position of read data transfer which uses the DAT line, or at the end bit position of the Write CRC Status.
RW 0x0
21 EDCRC 
              EDCRC - Data CRC Error (SD mode only)\n
              When set to 1, indicates detecting CRC error when transferring read data which uses the DAT line, or when detecting the Write CRC status having a value of other than 010.\n
              This bit will be set to 1 immediately when conflict on CMD line detected.\n
              The conflict is signalized by setting this bit and SRS12.EDT to 1.
RW 0x0
20 EDT 
              EDT - Data Timeout Error (SD mode only)\n
              When set to 1, indicates detecting one of the following timeout conditions:\n
              1. Busy timeout for the response with busy.\n
              2. Busy timeout after Write CRC status.\n
              3. Write CRC Status timeout.\n
              4. Read data timeout.\n
              This bit will be set to 1 immediately when conflict on CMD line conflict detected.
RW 0x0
19 ECI 
              ECI - Command Index Error (SD mode only)\n
              When set to 1, indicates that Index error occurs in the command response.
RW 0x0
18 ECEB 
              ECEB - Command End Bit Error (SD mode only)\n
              When set to 1, indicates detecting that the end bit of a command response is 0.
RW 0x0
17 ECCRC 
              ECCRC - Command CRC Error (SD mode only)\n
              When set to 1, indicates that command CRC error has occurred.
RW 0x0
16 ECT 
              ECT - Command Timeout Error\n
              When set to 1, indicates that no response was returned within 64 SDCLK cycles from the end bit of the command.
RW 0x0
15 EINT 
              EINT - Error Interrupt\n
              This bit is set if any of bits in range SRS12[31:16] is set;
              The software can check for an error by reading this single bit first.
RO 0x0
14 CQINT 
              CQINT - Command Queuing Interrupt\n
              This interrupt is asserted when at least one of the bits in CQIS register is set.
              This interrupt is cleared only by clearing the source interrupt in CQIS register.
RO 0x0
13 FXE 
              FXE - FX Event\n
              If SRS03.RECE is set to 1, and SRS03.RECT is set to 0 this interrupt indicates that 14th bit of response stored as 6th bit of SRS04 register is set to 1.\n
              If SRS03.RECE is set to 1 only next response with type R1 containing card status bit 14th equal 0 can clean this interrupt.\n
              If SRS03.RECE is set to 0, this interrupt indicates that 14th bit of response stored as 6th bit of SRS04 register is set to 1 except cases:\n
              1. Argument of CMD13 bit 15 is equal 1 - then response won't change value of this interrupt.\n
              2. Issued command does not have a response - then value of this interrupt won't change.\n
RO 0x0
12:9 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
8 CINT 
              CINT - Card Interrupt\n
              Indicates the card interrupt. CINT is not sampled by the card clock, so the interrupt can be detected even with SD clock stopped (SRS11.SDCE=0).
              Also, CINT is not cleared by writing 1. Instead, the software will clear the source of an interrupt inside the card.After detecting the Card Interrupt,
              the software will stop further interrupt detection by clearing SRS13.CINT_SE to 0.
              Then, the software will clear the interrupt source inside the card by using the appropriate commands.
              For the details, please refer to the SDIO Card Specification.\n
              After clearing the interrupt source, the card will stop to drive the interrupt signal to the host.
              Finally, when the interrupt service routine is finished, the interrupt detection can be enabled by setting SRS13.CINT_SE back to 1.
RO 0x0
7 CR 
              CR - Card Removal\n
              Generated when the SRS09.CI bit changes from 1 to 0, indicating card removal event.\n
              When read as 1, indicates that the card was removed from the slot.\n
              When read as 0, indicates that the card state is stable (still inserted or removed) or that the debouncing is in progress.
RW 0x0
6 CIN 
              CIN - Card Insertion\n
              Generated when the SRS09.CI bit changes from 0 to 1, indicating card insertion.\n
              When read as 1, indicates that the card was inserted to the slot.\n
              When read as 0, indicates that the card state is stable (still inserted or removed) or that the debouncing is in progress.
RW 0x0
5 BRR 
              BRR - Buffer Read Ready\n
              Generated when the BRE changes from 0 to 1, indicating that the data buffer can be read by the software.\n
              This field works differently in the SD Tuning Sequence, i.e. when Sampling Clock Select (SRS15.SCS) equals 1. It is set to 1 on the tune step completion despite of the step's result. As per the Standard, during the SD tuning, none of the interrupts is notified except Buffer Read Ready.
RW 0x0
4 BWR 
              BWR - Buffer Write Ready\n
              Generated when the BWE changes from 0 to 1, indicating that the data buffer can be written by the software.
RW 0x0
3 DMAINT 
              DMAINT - DMA Interrupt\n
              In SDMA mode, DMA interrupt is generated when the host controller detects the Host SDMA Buffer boundary.\n
              In ADMA mode, DMA interrupt is generated when the INT flag is set in a currently serviced ADMA descriptor.
RW 0x0
2 BGE 
              BGE - Block Gap Event\n
              Generated when the read/write transaction is stopped at a block gap as the result of setting SRS10.SBGR to 1.
RW 0x0
1 TC 
              TC - Transfer Complete\n
              SD Mode:\n
              Generated when the transfer which uses the DAT line is complete.
              Transfers which use the DAT line include the read/write transfers and commands with a busy response.\n
              In case of the read transfer, TC indicates that the entire data was transferred from the card to the host system (i.e. the host FIFO is empty after reading the last data block).\n
              In case of the write transfer, TC indicates that the entire data was transferred from the host to the card (i.e. the host FIFO is empty after writing the last data block),
              and the card accepted the data (busy signal released after the last block).
              In the case of the command with a busy response, TC indicates that the busy signal is released after the response.
RW 0x0
0 CC 
              CC - Command Complete\n
              Generated when the end bit of the response is received, except the response for Auto-CMD12 command. Auto-CMD12 command does not generate CC.
RW 0x0