SRS30 

         
            SRS30 ADMA3 ID Address 1
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x10808278

Size: 32

Offset: 0x78

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADMA3ID1

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADMA3ID1

RW 0x0

SRS30 Fields

Bit Name Description Access Reset
31:0 ADMA3ID1 
              ADMA3 Integrated Descriptor Address #1\n
              This field contains the physical address of the currently processed ADMA3 Integrated Descriptor address.
              The Host Driver will set this register with the ID table base address before it starts the ADMA3 transfers.
              The Host Driver should not write this register while the data transfer is active.
              While the ADMA3 engine is processing the descriptors list,
              the ADMA3ID value is always incremented to point the next ID to be fetched.
              The host ADMA3 engine ignores 2 or 3 least significant bits in this register
              when the 32-bit or 64-bit addressing is active, respectively.\n
              \n
              When ADMA3 uses 32-bit addressing mode, write to this register starts ADMA3.
RW 0x0