SRS20

         
            SRS20 - Force Event\n
            Each field of this register is related to the specific error status. Writing 1 to field will set the status error. This function is provided for SW debug purpose.


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808200`	`0x10808250`

Size: 32

Offset: 0x50

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_18` `RO 0x0`				`ERESP_FE` `WO 0x0`	`ETUNE_FE` `WO 0x0`	`EADMA_FE` `WO 0x0`	`EAC_FE` `WO 0x0`	`ECL_FE` `WO 0x0`	`EDEB_FE` `WO 0x0`	`EDCRC_FE` `WO 0x0`	`EDT_FE` `WO 0x0`	`ECI_FE` `WO 0x0`	`ECEB_FE` `WO 0x0`	`ECCRC_FE` `WO 0x0`	`ECT_FE` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_6` `RO 0x0`								`CNIACE_FE` `WO 0x0`	`Reserved_5` `RO 0x0`		`ACIE_FE` `WO 0x0`	`ACEBE_FE` `WO 0x0`	`ACCE_FE` `WO 0x0`	`ACTE_FE` `WO 0x0`	`ACNE_FE` `WO 0x0`

SRS20 Fields


Bit	Name	Description	Access	Reset
31:28	`Reserved_18`	Reserved bitfield added by Magillem	`RO`	`0x0`
27	`ERESP_FE`	ERESP_FE - Force Response Error Event	`WO`	`0x0`
26	`ETUNE_FE`	ETUNE_FE - Force Tuning Error Event	`WO`	`0x0`
25	`EADMA_FE`	EADMA_FE - Force ADMA Error Event	`WO`	`0x0`
24	`EAC_FE`	EAC_FE - Force Auto CMD Error Event	`WO`	`0x0`
23	`ECL_FE`	ECL_FE - Force Current Limit Error Event	`WO`	`0x0`
22	`EDEB_FE`	EDEB_FE - Force Data End Bit Error Event	`WO`	`0x0`
21	`EDCRC_FE`	EDCRC_FE - Force Data CRC Error Event	`WO`	`0x0`
20	`EDT_FE`	EDT_FE - Force Data Timeout Error Event	`WO`	`0x0`
19	`ECI_FE`	ECI_FE - Force Command Index Error Event	`WO`	`0x0`
18	`ECEB_FE`	ECEB_FE - Force Command End Bit Error Event	`WO`	`0x0`
17	`ECCRC_FE`	ECCRC_FE - Force Command CRC Error Event	`WO`	`0x0`
16	`ECT_FE`	ECT_FE - Force Command Timeout Error Event	`WO`	`0x0`
15:8	`Reserved_6`	Reserved bitfield added by Magillem	`RO`	`0x0`
7	`CNIACE_FE`	CNIACE_FE - Force Command Not Issued By Auto CMD12 Error Event	`WO`	`0x0`
6:5	`Reserved_5`	Reserved bitfield added by Magillem	`RO`	`0x0`
4	`ACIE_FE`	ACIE_FE - Force Auto CMD Index Error Event	`WO`	`0x0`
3	`ACEBE_FE`	ACEBE_FE - Force Auto CMD End Bit Error Event	`WO`	`0x0`
2	`ACCE_FE`	ACCE_FE - Force Auto CMD CRC Error Event	`WO`	`0x0`
1	`ACTE_FE`	ACTE_FE - Force Auto CMD Timeout Error Event	`WO`	`0x0`
0	`ACNE_FE`	ACNE_FE - Force Auto CMD12 Not Executed Event	`WO`	`0x0`