perpllgrp Summary

Contains registers with settings for the Peripheral PLL.

Base Address: 0x10D1007C


Register Address Offset	Bit Fields
`i_clk_mgr__clkmgr_csr__10d10000__perpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`
`en` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_28` `RO 0x3`				`i2c_emac2_clken` `RW 0x1`	`softphyclken` `RW 0x1`	`usb31clken` `RW 0x1`	`sptimer_1_clken` `RW 0x1`	`sptimer_0_clken` `RW 0x1`	`i2c_emac1_clken` `RW 0x1`	`uart_1_clken` `RW 0x1`	`uart_0_clken` `RW 0x1`	`i3c_1_clken` `RW 0x1`	`i3c_0_clken` `RW 0x1`	`i2c_emac0_clken` `RW 0x1`	`i2c_1_clken` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`i2c_0_clken` `RW 0x1`	`dmaclken` `RW 0x1`	`spis_1_clken` `RW 0x1`	`spis_0_clken` `RW 0x1`	`spim_1_clken` `RW 0x1`	`nandclken` `RW 0x1`	`spim_0_clken` `RW 0x1`	`usb2clken` `RW 0x1`	`psiclken` `RW 0x1`	`s2fuser1clken` `RW 0x1`	`sdmmcclken` `RW 0x1`	`gpiodben` `RW 0x1`	`emacptpen` `RW 0x1`	`emac2en` `RW 0x1`	`emac1en` `RW 0x1`	`emac0en` `RW 0x1`
`ens` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_28` `RO 0x0`				`i2c_emac2_clken` `RW 0x0`	`softphyclken` `RW 0x0`	`usb31clken` `RW 0x0`	`sptimer_1_clken` `RW 0x0`	`sptimer_0_clken` `RW 0x0`	`i2c_emac1_clken` `RW 0x0`	`uart_1_clken` `RW 0x0`	`uart_0_clken` `RW 0x0`	`i3c_1_clken` `RW 0x0`	`i3c_0_clken` `RW 0x0`	`i2c_emac0_clken` `RW 0x0`	`i2c_1_clken` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`i2c_0_clken` `RW 0x0`	`dmaclken` `RW 0x0`	`spis_1_clken` `RW 0x0`	`spis_0_clken` `RW 0x0`	`spim_1_clken` `RW 0x0`	`nandclken` `RW 0x0`	`spim_0_clken` `RW 0x0`	`usb2clken` `RW 0x0`	`psiclken` `RW 0x0`	`s2fuser1clken` `RW 0x0`	`sdmmcclken` `RW 0x0`	`gpiodben` `RW 0x0`	`emacptpen` `RW 0x0`	`emac2en` `RW 0x0`	`emac1en` `RW 0x0`	`emac0en` `RW 0x0`
`enr` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_28` `RO 0x0`				`i2c_emac2_clken` `RW 0x0`	`softphyclken` `RW 0x0`	`usb31clken` `RW 0x0`	`sptimer_1_clken` `RW 0x0`	`sptimer_0_clken` `RW 0x0`	`i2c_emac1_clken` `RW 0x0`	`uart_1_clken` `RW 0x0`	`uart_0_clken` `RW 0x0`	`i3c_1_clken` `RW 0x0`	`i3c_0_clken` `RW 0x0`	`i2c_emac0_clken` `RW 0x0`	`i2c_1_clken` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`i2c_0_clken` `RW 0x0`	`dmaclken` `RW 0x0`	`spis_1_clken` `RW 0x0`	`spis_0_clken` `RW 0x0`	`spim_1_clken` `RW 0x0`	`nandclken` `RW 0x0`	`spim_0_clken` `RW 0x0`	`usb2clken` `RW 0x0`	`psiclken` `RW 0x0`	`s2fuser1clken` `RW 0x0`	`sdmmcclken` `RW 0x0`	`gpiodben` `RW 0x0`	`emacptpen` `RW 0x0`	`emac2en` `RW 0x0`	`emac1en` `RW 0x0`	`emac0en` `RW 0x0`
`bypass` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`								`usb31` `RW 0x1`	`psiref` `RW 0x1`	`s2fuser1` `RW 0x1`	`Reserved_4` `RO 0x1`	`gpiodb` `RW 0x1`	`emacptp` `RW 0x1`	`emacb` `RW 0x1`	`emaca` `RW 0x1`
`bypasss` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`								`usb31` `RW 0x1`	`psiref` `RW 0x1`	`s2fuser1` `RW 0x1`	`Reserved_4` `RO 0x1`	`gpiodb` `RW 0x1`	`emacptp` `RW 0x1`	`emacb` `RW 0x1`	`emaca` `RW 0x1`
`bypassr` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`								`usb31` `RW 0x1`	`psiref` `RW 0x1`	`s2fuser1` `RW 0x1`	`Reserved_4` `RO 0x1`	`gpiodb` `RW 0x1`	`emacptp` `RW 0x1`	`emacb` `RW 0x1`	`emaca` `RW 0x1`
`emacctl` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`			`emac2sel` `RW 0x0`	`emac1sel` `RW 0x0`	`emac0sel` `RW 0x0`	`Reserved_0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`gpiodiv` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`gpiodbclk` `RW 0x1`
`pllglob` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_12` `RO 0x0`		`clr_lostlock_bypass` `RW 0x0`	`lostlock_bypass_en` `RW 0x1`	`modclkdiv` `RW 0x5`				`Reserved_9` `RO 0x0`		`fastrefclk` `RW 0x0`	`disctrl` `RW 0x0`	`clksync` `RW 0x0`	`pwrgatectrl` `RW 0x0`	`psrc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`		`drefclkdiv` `RW 0x0`		`arefclkdiv` `RW 0x1`				`Reserved_2` `RO 0x0`						`rst_n` `RW 0x0`	`pd_n` `RW 0x1`
`fdbck` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`								`fdiv` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`fdiv` `RW 0x0`
`mem` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`					`err` `RO 0x0`	`wr` `RW 0x0`	`req` `RW 0x0`	`wdat` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`addr` `RW 0x0`
`memstat` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`rdata` `RO 0x0`
`vcocalib` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`				`clr` `RW 0x0`	`banksel` `RW 0x0`		`Reserved_2` `RO 0x0`	`mscnt` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x2`						`hscnt` `RW 0x74`
`pllc0` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x5`
`pllc1` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x5`
`pllc2` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x7D`
`pllc3` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x6`
`pllm` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`						`mdiv` `RW 0x78`
`fhop` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`															`ack` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`req` `RW 0x0`	`Reserved_1` `RO 0x0`						`dir` `RW 0x0`
`ssc` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`stat` `RO 0x0`	`Reserved_1` `RO 0x0`							`en` `RW 0x0`
`lostlock` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`bypass_cleared` `RW 0x0`