emacctl 

         Selects the source for emac0/1/2_clk either from emaca_free_clk or from emacb_free_clk.
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__perpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D1007C 0x10D10094

Size: 32

Offset: 0x18

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_3

RO 0x0

emac2sel

RW 0x0

emac1sel

RW 0x0

emac0sel

RW 0x0

Reserved_0

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_0

RO 0x0

emacctl Fields

Bit Name Description Access Reset
31:29 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
28 emac2sel 
Selects the source for emac2_clk as either emaca_free_clk or emacb_free_clk.
Value Description
0 EMAC A
1 EMAC B
RW 0x0
27 emac1sel 
Selects the source for emac1_clk as either emaca_free_clk or emacb_free_clk.
Value Description
0 EMAC A
1 EMAC B
RW 0x0
26 emac0sel 
Selects the source for emac0_clk as either emaca_free_clk or emacb_free_clk.
Value Description
0 EMAC A
1 EMAC B
RW 0x0
25:0 Reserved_0 
Reserved bitfield added by Magillem
 RO 0x0