fdbck

         VCO freq register counters


Module Instance	Base Address	Register Address
`i_clk_mgr__clkmgr_csr__10d10000__perpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`	`0x10D1007C`	`0x10D100A0`

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`								`fdiv` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`fdiv` `RW 0x0`

fdbck Fields

Bit Name Description Access Reset

31:24

Bit	Name	Description	Access	Reset
31:24	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
23:0	`fdiv`	Fractional synthesizer center frequency control word. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at Reset or PD state. It can be only set while the HP PLL IP is at Reset or PD state. It cannot be switched dynamically. If ictl_pll_fastref_en_nt is 1'b0, Fref_eff <=200MHz If ictl_pll_fastref_en_nt is 1'b1, Fref_eff <=312MHz Fref_eff = (Fref/ictl_pll_arefdiv_nt_[3:0]) Freq_mul: It is a multiplier that consists of an integer portion and a fraction portion. If ictl_pll_fefb_en_nt = 0 and ictl_pll_extfb_en_nt = 0 Freq_mul = (ictl_pll_mdiv_nt_[9:0]) + ((ictl_pll_fdiv_nt_[23:0])/(2^24)) If ictl_pll_fefb_en_nt = 1 and ictl_pll_extfb_en_nt = 0 Freq_mul = (ictl_pll_mdiv_nt_[9:0]) + ((ictl_pll_fdiv_nt_[23:0])/(2^24)) * ictl_pll_clkslice0_div_[10:0] If ictl_pll_fefb_en_nt = 0 and ictl_pll_extfb_en_nt = 1 Freq_mul = (ictl_pll_mdiv_nt_[9:0]) + ((ictl_pll_fdiv_nt_[23:0])/(2^24)) * ictl_pll_clkslice<0/1/2/3>_div_[10:0] HP PLL Voltage-Controlled Oscillator (VCO) Output clock frequency is equal to PLL reference clock effective frequency multiplied with frequency multiplier. Fsynthvco = Freq_mul * Fref_effective If ictl_pll_fastref_en_nt = 1'b0, 600MHz >= ((Fsynthvco)/(ictl_pll_moddiv_nt_[3:0])) >= 3* Fref_eff If ictl_pll_fastref_en_nt = 1'b1, 600MHz >= ((Fsynthvco)/(ictl_pll_moddiv_nt_[3:0])) >= 1.5* Fref_eff Fock_pll_clkslice<0,1,2,3> = (Fsynthvco)/(ictl_pll_clkslice<0,1,2,3>_div_[10:0])	`RW`	`0x0`

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

23:0

fdiv

Fractional synthesizer center frequency control word. 
The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at Reset or PD state. 
It can be only set while the HP PLL IP is at Reset or PD state. It cannot be switched dynamically.

If ictl_pll_fastref_en_nt is 1'b0, Fref_eff <=200MHz
If ictl_pll_fastref_en_nt is 1'b1, Fref_eff <=312MHz

Fref_eff = (Fref/ictl_pll_arefdiv_nt_[3:0])

Freq_mul: It is a multiplier that consists of an integer portion and a fraction portion.
If ictl_pll_fefb_en_nt = 0 and ictl_pll_extfb_en_nt = 0
Freq_mul = (ictl_pll_mdiv_nt_[9:0]) + ((ictl_pll_fdiv_nt_[23:0])/(2^24))

If ictl_pll_fefb_en_nt = 1 and ictl_pll_extfb_en_nt = 0
Freq_mul = (ictl_pll_mdiv_nt_[9:0]) + ((ictl_pll_fdiv_nt_[23:0])/(2^24)) * ictl_pll_clkslice0_div_[10:0]

If ictl_pll_fefb_en_nt = 0 and ictl_pll_extfb_en_nt = 1
Freq_mul = (ictl_pll_mdiv_nt_[9:0]) + ((ictl_pll_fdiv_nt_[23:0])/(2^24)) * ictl_pll_clkslice<0/1/2/3>_div_[10:0]

HP PLL Voltage-Controlled Oscillator (VCO) Output clock frequency is equal to PLL reference clock effective frequency multiplied with frequency multiplier.
Fsynthvco = Freq_mul * Fref_effective

If ictl_pll_fastref_en_nt = 1'b0,
600MHz >= ((Fsynthvco)/(ictl_pll_moddiv_nt_[3:0])) >= 3* Fref_eff

If ictl_pll_fastref_en_nt = 1'b1,
600MHz >= ((Fsynthvco)/(ictl_pll_moddiv_nt_[3:0])) >= 1.5* Fref_eff

Fock_pll_clkslice<0,1,2,3> = (Fsynthvco)/(ictl_pll_clkslice<0,1,2,3>_div_[10:0])

RW

0x0