en 

         Contains fields that control clock enables for clocks derived from the Peripheral PLL.
1: The clock is enabled.
0: The clock is disabled.
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__perpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D1007C 0x10D1007C

Size: 32

Offset: 0x

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_28

RO 0x3

i2c_emac2_clken

RW 0x1

softphyclken

RW 0x1

usb31clken

RW 0x1

sptimer_1_clken

RW 0x1

sptimer_0_clken

RW 0x1

i2c_emac1_clken

RW 0x1

uart_1_clken

RW 0x1

uart_0_clken

RW 0x1

i3c_1_clken

RW 0x1

i3c_0_clken

RW 0x1

i2c_emac0_clken

RW 0x1

i2c_1_clken

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

i2c_0_clken

RW 0x1

dmaclken

RW 0x1

spis_1_clken

RW 0x1

spis_0_clken

RW 0x1

spim_1_clken

RW 0x1

nandclken

RW 0x1

spim_0_clken

RW 0x1

usb2clken

RW 0x1

psiclken

RW 0x1

s2fuser1clken

RW 0x1

sdmmcclken

RW 0x1

gpiodben

RW 0x1

emacptpen

RW 0x1

emac2en

RW 0x1

emac1en

RW 0x1

emac0en

RW 0x1

en Fields

Bit Name Description Access Reset
31:28 Reserved_28 
Reserved bitfield added by Magillem
 RO 0x3
27 i2c_emac2_clken 
Enables i2c_emac2 peripheral clock.   This enable goes outside of the Clock Manger to the i2c_emac2 directly.
 RW 0x1
26 softphyclken 
Enables softphy peripheral clock.   This enable goes outside of the Clock Manger to the softphy directly.
 RW 0x1
25 usb31clken 
Enables usb31 peripheral clock.   This enable goes outside of the Clock Manger to the usb31 directly.
 RW 0x1
24 sptimer_1_clken 
Enables sptimer_1 peripheral clock.   This enable goes outside of the Clock Manger to the sptimer_1 directly.
 RW 0x1
23 sptimer_0_clken 
Enables sptimer_0 peripheral clock.   This enable goes outside of the Clock Manger to the sptimer_0 directly.
 RW 0x1
22 i2c_emac1_clken 
Enables i2c_emac1 peripheral clock.   This enable goes outside of the Clock Manger to the i2c_emac1 directly.
 RW 0x1
21 uart_1_clken 
Enables uart_1 peripheral clock.   This enable goes outside of the Clock Manger to the uart_1 directly.
 RW 0x1
20 uart_0_clken 
Enables uart_0 peripheral clock.   This enable goes outside of the Clock Manger to the uart_0 directly.
 RW 0x1
19 i3c_1_clken 
Enables i3c_1 peripheral clock.   This enable goes outside of the Clock Manger to the i3c_1 directly.
 RW 0x1
18 i3c_0_clken 
Enables i3c_0 peripheral clock.   This enable goes outside of the Clock Manger to the i3c_0 directly.
 RW 0x1
17 i2c_emac0_clken 
Enables i2c_emac0 peripheral clock.   This enable goes outside of the Clock Manger to the i2c_emac0 directly.
 RW 0x1
16 i2c_1_clken 
Enables i2c_1 peripheral clock.   This enable goes outside of the Clock Manger to the i2c_1 directly.
 RW 0x1
15 i2c_0_clken 
Enables i2c_0 peripheral clock.   This enable goes outside of the Clock Manger to the I2C0 directly.
 RW 0x1
14 dmaclken 
Enables DMA peripheral clock.   This enable goes outside of the Clock Manger to the DMA directly.
 RW 0x1
13 spis_1_clken 
Enables SPIS1 peripheral clock.   This enable goes outside of the Clock Manger to the SPIS1 directly.
 RW 0x1
12 spis_0_clken 
Enables SPIS0 peripheral clock.   This enable goes outside of the Clock Manger to the SPIS0 directly.
 RW 0x1
11 spim_1_clken 
Enables SPIM1peripheral clock.   This enable goes outside of the Clock Manger to the SPIM1 directly.
 RW 0x1
10 nandclken 
Enables NAND peripheral clock.   This enable goes outside of the Clock Manger to the NAND directly.
 RW 0x1
9 spim_0_clken 
Enables SPIM0 Master peripheral clock.   This enable goes outside of the Clock Manger to the SPIM0 directly.
 RW 0x1
8 usb2clken 
Enables USB2-OTG peripheral clock.   This enable goes outside of the Clock Manger to the USB2-OTG directly.
 RW 0x1
7 psiclken 
Enables psi_ref clock.
RW 0x1
6 s2fuser1clken 
Enables clock s2f_user1_clk output
 RW 0x1
5 sdmmcclken 
Enables SDMMC peripheral clock.   This enable goes outside of the Clock Manger to the SDMMC directly.
 RW 0x1
4 gpiodben 
Enables clock gpio_db_clk output
 RW 0x1
3 emacptpen 
Enables clock emac_ptp_clk output
 RW 0x1
2 emac2en 
Enables clock emac2_clk output
 RW 0x1
1 emac1en 
Enables clock emac1_clk output
 RW 0x1
0 emac0en 
Enables clock emac0_clk output
 RW 0x1