bypass 

         Contains fields that control bypass for clocks derived from the Peripheral PLL.
1: The clock is bypassed.
0: The clock is derived from the 5:1 active mux.
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__perpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D1007C 0x10D10088

Size: 32

Offset: 0xC

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_7

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_7

RO 0x0

usb31

RW 0x1

psiref

RW 0x1

s2fuser1

RW 0x1

Reserved_4

RO 0x1

gpiodb

RW 0x1

emacptp

RW 0x1

emacb

RW 0x1

emaca

RW 0x1

bypass Fields

Bit Name Description Access Reset
31:8 Reserved_7 
Reserved bitfield added by Magillem
 RO 0x0
7 usb31 
If set, the USB31 clock will be bypassed to the input clock reference of the Peripheral PLL.
 RW 0x1
6 psiref 
If set, the psi_ref_clk will be bypassed to the input clock reference of the Peripheral PLL.
 RW 0x1
5 s2fuser1 
If set, the s2f_user1_clk will be bypassed to the input clock reference of the Peripheral PLL.
 RW 0x1
4 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x1
3 gpiodb 
If set, the gpio_db_clk will be bypassed to the input clock reference of the Peripheral PLL.
 RW 0x1
2 emacptp 
If set, the emac_ptp_clk will be bypassed to the input clock reference of the Peripheral PLL.
 RW 0x1
1 emacb 
If set, the emacb_free_clk will be bypassed to the input clock reference of the Main PLL.
 RW 0x1
0 emaca 
If set, the emaca_free_clk will be bypassed to the input clock reference of the Main PLL.
 RW 0x1