lostlock 

         To enable the keep alive clock to appear on the clock slice outputs when PLL lock is lost. By default, the clock slices are muted (bit = 0).
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__perpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D1007C 0x10D100CC

Size: 32

Offset: 0x50

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x0

bypass_cleared

RW 0x0

lostlock Fields

Bit Name Description Access Reset
31:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 bypass_cleared 
When all the bypass_en asserted due to loss of PLL  lock from all the channels go low this bit gets set to 1. 

This is should clear clr_lostlock_bypass automatically. Before setting clr_lostlock_bypass, SW should clear this register.
 RW 0x0