i3c_main_master Summary

DWC_mipi_i3c

Base Address: 0x10DA0000


Register Address Offset	Bit Fields
`i_i3c_main_master__i3c_m_apb_slv__10da0000__DWC_mipi_i3c_block__SEG_L4_SP_i3c0_0x0_0x1000`
`DEVICE_CTRL` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ENABLE` `RW 0x0`	`RESUME` `RW 0x0`	`ABORT` `RW 0x0`	`DMA_ENABLE` `RW 0x0`	`Reserved_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`							`HOT_JOIN_CTRL` `RW 0x0`	`I2C_SLAVE_PRESENT` `RW 0x0`	`Reserved_1` `RO 0x0`						`IBA_INCLUDE` `RW 0x0`
`DEVICE_ADDR` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DYNAMIC_ADDR_VALID` `RW 0x1`	`Reserved_1` `RO 0x0`								`DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`HW_CAPABILITY` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_8` `RO 0x0`												`SLV_IBI_CAP` `RO 0x0`	`SLV_HJ_CAP` `RO 0x0`	`DMA_EN` `RO 0x1`	`HDR_TX_CLOCK_PERIOD` `RO 0x28`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`HDR_TX_CLOCK_PERIOD` `RO 0x28`					`CLOCK_PERIOD` `RO 0x8`						`HDR_TS_EN` `RO 0x0`	`HDR_DDR_EN` `RO 0x0`	`DEVICE_ROLE_CONFIG` `RO 0x1`
`COMMAND_QUEUE_PORT` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`COMMAND` `WO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`COMMAND` `WO 0x0`
`RESPONSE_QUEUE_PORT` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESPONSE` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESPONSE` `RO 0x0`
`TX_DATA_PORT` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TX_DATA_PORT` `WO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TX_DATA_PORT` `WO 0x0`
`IBI_QUEUE_STATUS` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`IBI_STS` `RO 0x0`				`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`IBI_ID` `RO 0x0`								`DATA_LENGTH` `RO 0x0`
`QUEUE_THLD_CTRL` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`IBI_STATUS_THLD` `RW 0x1`								`IBI_DATA_THLD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESP_BUF_THLD` `RW 0x1`								`CMD_EMPTY_BUF_THLD` `RW 0x1`
`DATA_BUFFER_THLD_CTRL` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`					`RX_START_THLD` `RW 0x1`			`Reserved_3` `RO 0x0`					`TX_START_THLD` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`					`RX_BUF_THLD` `RW 0x1`			`Reserved_1` `RO 0x0`					`TX_EMPTY_BUF_THLD` `RW 0x1`
`IBI_QUEUE_CTRL` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`												`NOTIFY_SIR_REJECTED` `RW 0x0`	`Reserved_1` `RO 0x0`		`NOTIFY_HJ_REJECTED` `RW 0x0`
`RESET_CTRL` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_6` `RO 0x0`										`IBI_QUEUE_RST` `RW 0x0`	`RX_FIFO_RST` `RW 0x0`	`TX_FIFO_RST` `RW 0x0`	`RESP_QUEUE_RST` `RW 0x0`	`CMD_QUEUE_RST` `RW 0x0`	`SOFT_RST` `RW 0x0`
`SLV_EVENT_STATUS` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`								`MWL_UPDATED` `RW 0x0`	`MRL_UPDATED` `RW 0x0`	`ACTIVITY_STATE` `RO 0x0`		`Reserved_0` `RO 0x0`
`INTR_STATUS` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`TRANSFER_ERR_STS` `RW 0x0`	`Reserved_6` `RO 0x0`			`TRANSFER_ABORT_STS` `RW 0x0`	`RESP_READY_STS` `RO 0x0`	`CMD_QUEUE_READY_STS` `RO 0x0`	`IBI_THLD_STS` `RO 0x0`	`RX_THLD_STS` `RO 0x0`	`TX_THLD_STS` `RO 0x0`
`INTR_STATUS_EN` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`TRANSFER_ERR_STS_EN` `RW 0x0`	`Reserved_6` `RO 0x0`			`TRANSFER_ABORT_STS_EN` `RW 0x0`	`RESP_READY_STS_EN` `RW 0x0`	`CMD_QUEUE_READY_STS_EN` `RW 0x0`	`IBI_THLD_STS_EN` `RW 0x0`	`RX_THLD_STS_EN` `RW 0x0`	`TX_THLD_STS_EN` `RW 0x0`
`INTR_SIGNAL_EN` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`TRANSFER_ERR_SIGNAL_EN` `RW 0x0`	`Reserved_6` `RO 0x0`			`TRANSFER_ABORT_SIGNAL_EN` `RW 0x0`	`RESP_READY_SIGNAL_EN` `RW 0x0`	`CMD_QUEUE_READY_SIGNAL_EN` `RW 0x0`	`IBI_THLD_SIGNAL_EN` `RW 0x0`	`RX_THLD_SIGNAL_EN` `RW 0x0`	`TX_THLD_SIGNAL_EN` `RW 0x0`
`INTR_FORCE` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `WO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `WO 0x0`						`TRANSFER_ERR_FORCE_EN` `WO 0x0`	`Reserved_6` `WO 0x0`			`TRANSFER_ABORT_FORCE_EN` `WO 0x0`	`RESP_READY_FORCE_EN` `WO 0x0`	`CMD_QUEUE_READY_FORCE_EN` `WO 0x0`	`IBI_THLD_FORCE_EN` `WO 0x0`	`RX_THLD_FORCE_EN` `WO 0x0`	`TX_THLD_FORCE_EN` `WO 0x0`
`QUEUE_STATUS_LEVEL` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`			`IBI_STS_CNT` `RO 0x0`					`IBI_BUF_BLR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESP_BUF_BLR` `RO 0x0`								`CMD_QUEUE_EMPTY_LOC` `RO 0x0`
`DATA_BUFFER_STATUS_LEVEL` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`								`RX_BUF_BLR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`TX_BUF_EMPTY_LOC` `RO 0x20`
`PRESENT_STATE` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`			`MASTER_IDLE` `RO 0x1`	`CMD_TID` `RO 0x0`				`Reserved_5` `RO 0x0`		`CM_TFR_ST_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`		`CM_TFR_STS` `RO 0x0`						`Reserved_3` `RO 0x0`					`CURRENT_MASTER` `RO 0x0`	`SDA_LINE_SIGNAL_LEVEL` `RO 0x1`	`SCL_LINE_SIGNAL_LEVEL` `RO 0x1`
`DEVICE_ADDR_TABLE_POINTER` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEV_ADDR_TABLE_DEPTH` `RO 0xB`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`P_DEV_ADDR_TABLE_START_ADDR` `RO 0x280`
`DEV_CHAR_TABLE_POINTER` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`										`PRESENT_DEV_CHAR_TABLE_INDX` `RW 0x0`			`DEV_CHAR_TABLE_DEPTH` `RO 0x20`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DEV_CHAR_TABLE_DEPTH` `RO 0x20`				`P_DEV_CHAR_TABLE_START_ADDR` `RO 0x200`
`VENDOR_SPECIFIC_REG_POINTER` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`P_VENDOR_REG_START_ADDR` `RO 0xB0`
`DEVICE_CTRL_EXTENDED` `0x176` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`														`DEV_OPERATION_MODE` `RW 0x0`
`SCL_I3C_OD_TIMING` `0x180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`								`I3C_OD_HCNT` `RW 0xA`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`I3C_OD_LCNT` `RW 0x10`
`SCL_I3C_PP_TIMING` `0x184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`								`I3C_PP_HCNT` `RW 0xA`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`I3C_PP_LCNT` `RW 0xA`
`SCL_I2C_FM_TIMING` `0x188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`I2C_FM_HCNT` `RW 0x10`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`I2C_FM_LCNT` `RW 0x10`
`SCL_I2C_FMP_TIMING` `0x192` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`								`I2C_FMP_HCNT` `RW 0x10`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`I2C_FMP_LCNT` `RW 0x10`
`SCL_EXT_LCNT_TIMING` `0x200` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`I3C_EXT_LCNT_4` `RW 0x20`								`I3C_EXT_LCNT_3` `RW 0x20`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`I3C_EXT_LCNT_2` `RW 0x20`								`I3C_EXT_LCNT_1` `RW 0x20`
`SCL_EXT_TERMN_LCNT_TIMING` `0x204` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`I3C_EXT_TERMN_LCNT` `RW 0x0`
`SDA_HOLD_SWITCH_DLY_TIMING` `0x208` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`													`SDA_TX_HOLD` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`BUS_FREE_AVAIL_TIMING` `0x212` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BUS_FREE_TIME` `RW 0x20`
`I3C_VER_ID` `0x224` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`I3C_VER_ID` `RO 0x3130302A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`I3C_VER_ID` `RO 0x3130302A`
`I3C_VER_TYPE` `0x228` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`I3C_VER_TYPE` `RO 0x6C633033`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`I3C_VER_TYPE` `RO 0x6C633033`
`QUEUE_SIZE_CAPABILITY` `0x232` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`												`IBI_BUF_SIZE` `RO 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESP_BUF_SIZE` `RO 0x1`				`CMD_BUF_SIZE` `RO 0x2`				`RX_BUF_SIZE` `RO 0x4`				`TX_BUF_SIZE` `RO 0x4`
`DEV_CHAR_TABLE1_LOC1` `0x512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE1_LOC2` `0x516` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE1_LOC3` `0x520` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE1_LOC4` `0x524` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_CHAR_TABLE2_LOC1` `0x528` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE2_LOC2` `0x532` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE2_LOC3` `0x536` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE2_LOC4` `0x540` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_CHAR_TABLE3_LOC1` `0x544` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE3_LOC2` `0x548` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE3_LOC3` `0x552` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE3_LOC4` `0x556` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_CHAR_TABLE4_LOC1` `0x560` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE4_LOC2` `0x564` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE4_LOC3` `0x568` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE4_LOC4` `0x572` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_CHAR_TABLE5_LOC1` `0x576` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE5_LOC2` `0x580` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE5_LOC3` `0x584` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE5_LOC4` `0x588` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_CHAR_TABLE6_LOC1` `0x592` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE6_LOC2` `0x596` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE6_LOC3` `0x600` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE6_LOC4` `0x604` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_CHAR_TABLE7_LOC1` `0x608` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE7_LOC2` `0x612` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE7_LOC3` `0x616` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE7_LOC4` `0x620` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_CHAR_TABLE8_LOC1` `0x624` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LSB_PROVISIONAL_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE8_LOC2` `0x628` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MSB_PROVISIONAL_ID` `RO 0x0`
`DEV_CHAR_TABLE8_LOC3` `0x632` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCR` `RO 0x0`								`DCR` `RO 0x0`
`DEV_CHAR_TABLE8_LOC4` `0x636` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`DEV_DYNAMIC_ADDR` `RO 0x0`
`DEV_ADDR_TABLE1_LOC1` `0x640` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE2_LOC1` `0x644` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE3_LOC1` `0x648` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE4_LOC1` `0x652` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE5_LOC1` `0x656` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE6_LOC1` `0x660` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE7_LOC1` `0x664` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE8_LOC1` `0x668` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE9_LOC1` `0x672` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE10_LOC1` `0x676` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`
`DEV_ADDR_TABLE11_LOC1` `0x680` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DEVICE` `RW 0x0`	`DEV_NACK_RETRY_CNT` `RW 0x0`		`Reserved_6` `RO 0x0`					`DEV_DYNAMIC_ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`MR_REJECT` `RW 0x0`	`SIR_REJECT` `RW 0x0`	`IBI_WITH_DATA` `RW 0x0`	`IBI_PEC_EN` `RW 0x0`	`Reserved_1` `RO 0x0`				`STATIC_ADDRESS` `RW 0x0`