HW_CAPABILITY 

         
Hardware Capability register 

This register reflects the configured capabilities of DWC_mipi_i3c.
Module Instance Base Address Register Address
i_i3c_main_master__i3c_m_apb_slv__10da0000__DWC_mipi_i3c_block__SEG_L4_SP_i3c0_0x0_0x1000 0x10DA0000 0x10DA0008

Size: 32

Offset: 0x8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_8

RO 0x0

SLV_IBI_CAP

RO 0x0

SLV_HJ_CAP

RO 0x0

DMA_EN

RO 0x1

HDR_TX_CLOCK_PERIOD

RO 0x28

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HDR_TX_CLOCK_PERIOD

RO 0x28

CLOCK_PERIOD

RO 0x8

HDR_TS_EN

RO 0x0

HDR_DDR_EN

RO 0x0

DEVICE_ROLE_CONFIG

RO 0x1

HW_CAPABILITY Fields

Bit Name Description Access Reset
31:20 Reserved_8 
Reserved bitfield added by Magillem
 RO 0x0
19 SLV_IBI_CAP 
Reflects the IC_SLV_IBI Configurable Parameter.

Specifies slave's capability to initiate slave interrupt requests.
RO 0x0
18 SLV_HJ_CAP 
Reflects the IC_SLV_HJ Configurable Parameter.

Specifies slave's capability to initiate Hot-join request.
RO 0x0
17 DMA_EN 
Reflects the IC_HAS_DMA Configurable Parameter.

Specifies whether controller is configured to have DMA handshaking interface.
RO 0x1
16:11 HDR_TX_CLOCK_PERIOD 
Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter.
RO 0x28
10:5 CLOCK_PERIOD 
Reflects the IC_CLK_PERIOD Configurable Parameter
RO 0x8
4 HDR_TS_EN 
Reflects the IC_SPEED_HDR_TS Configurable Parameter.

Specifies the Controllers  capability to perform HDR-TS transfers.
 - 0: HDR-TS not supported
 - 1: HDR-TS supported
RO 0x0
3 HDR_DDR_EN 
Reflects the IC_SPEED_HDR_DDR Configurable Parameter.

Specifies the Controllers capability to perform HDR-DDR transfers.
 - 0: HDR-DDR not supported
 - 1: HDR-DDR supported
RO 0x0
2:0 DEVICE_ROLE_CONFIG 
Reflects the IC_DEVICE_ROLE Configurable Parameter.

Specifies the configured role of DWC_mipi_i3c controller
 - 1: Master Only
 - 2: Programmable Master-Slave
 - 3: Secondary Master
 - 4: Slave Only
RO 0x1