RESET_CTRL 

         
This Register is used for general software reset and for individual buffer reset.
Module Instance Base Address Register Address
i_i3c_main_master__i3c_m_apb_slv__10da0000__DWC_mipi_i3c_block__SEG_L4_SP_i3c0_0x0_0x1000 0x10DA0000 0x10DA0034

Size: 32

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_6

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_6

RO 0x0

IBI_QUEUE_RST

RW 0x0

RX_FIFO_RST

RW 0x0

TX_FIFO_RST

RW 0x0

RESP_QUEUE_RST

RW 0x0

CMD_QUEUE_RST

RW 0x0

SOFT_RST

RW 0x0

RESET_CTRL Fields

Bit Name Description Access Reset
31:6 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
5 IBI_QUEUE_RST 
IBI Queue Software Reset.

This bit is only used in master mode of operation.

Write 1'b1 to this bit to exercise IBI Queue reset
This bit is cleared automatically once the IBI Queue reset is completed.
RW 0x0
4 RX_FIFO_RST 
Receive Buffer Software Reset.

Write 1'b1 to this bit to exercise Receive Buffer reset.
This bit is cleared automatically once the Receive buffer reset is completed.
RW 0x0
3 TX_FIFO_RST 
Transmit Buffer Software Reset

Write 1'b1 to this bit to exercise Transmit Buffer reset.
This bit is cleared automatically once the Transmit Buffer reset is completed.
RW 0x0
2 RESP_QUEUE_RST 
Response Queue Software Reset

Write 1'b1 to this bit to exercise Response Queue reset.
This bit is cleared automatically once the Response Queue reset is complete.
RW 0x0
1 CMD_QUEUE_RST 
Command Queue Software Reset

Write 1'b1 to this bit to exercise Command Queue reset.
This bit is cleared automatically once the Command Queue reset is complete.
RW 0x0
0 SOFT_RST 
Core Software Reset. 

Write 1'b1 to this bit to exercise software reset.
This resets all Buffers - Receive, Transmit, Command, and Response
This bit is cleared automatically once the core reset is complete.
RW 0x0