PRESENT_STATE

         
The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register. This register is relevant in both master and slave mode of operation and is meant to be used to get debug information related to the controllers internal states.


Module Instance	Base Address	Register Address
`i_i3c_main_master__i3c_m_apb_slv__10da0000__DWC_mipi_i3c_block__SEG_L4_SP_i3c0_0x0_0x1000`	`0x10DA0000`	`0x10DA0054`

Size: 32

Offset: 0x54

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_7` `RO 0x0`			`MASTER_IDLE` `RO 0x1`	`CMD_TID` `RO 0x0`				`Reserved_5` `RO 0x0`		`CM_TFR_ST_STS` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_4` `RO 0x0`		`CM_TFR_STS` `RO 0x0`						`Reserved_3` `RO 0x0`					`CURRENT_MASTER` `RO 0x0`	`SDA_LINE_SIGNAL_LEVEL` `RO 0x1`	`SCL_LINE_SIGNAL_LEVEL` `RO 0x1`

PRESENT_STATE Fields

Bit Name Description Access Reset

31:29

Reserved_7

Reserved bitfield added by Magillem

RO

0x0

MASTER_IDLE

This field reflects whether the Master Controller is in Idle state or not. This bit is set when all the Queues(Command , Response, IBI) and Buffers(Transmit and Receive) are empty along with the Master State machine is in Idle state.

Value	Description
0x0	Master Controller is not in IDLE State
0x1	Master Controller is in IDLE State.

RO

0x1

27:24

CMD_TID

This field reflects the Transaction-ID of the current executing command.

RO

0x0

23:22

Reserved_5

Reserved bitfield added by Magillem

RO

0x0

21:16

CM_TFR_ST_STS

Current Master Transfer State Status. 

Indicates the state of current transfer currently executing by the DWC_mipi_i3c controller.
This is valid in Master mode only.

 - 6'h0: IDLE (Controller is Idle state, waiting for commands from application or Slave initated In-band Interrupt)
 - 6'h1: START Generation State.
 - 6'h2: RESTART Generation State.
 - 6'h3: STOP Generation State.
 - 6'h4: START Hold Generation for the Slave Initiated START State.
 - 6'h5: Broadcast Write Address Header(7'h7E,W) Generation State.
 - 6'h6: Broadcast Read Address Header(7'h7E,R) Generation State.
 - 6'h7: Dynamic Address Assignment State.
 - 6'h8: Slave Address Generation State.
 - 6'hB: CCC Byte Generation State.
 - 6'hC: HDR Command Generation State.
 - 6'hD: Write Data Transfer State.
 - 6'hE: Read Data Transfer State.
 - 6'hF: In-Band Interrupt(SIR) Read Data State.
 - 6'h10:  In-Band Interrupt Auto-Disable State
 - 6'h11: HDR-DDR CRC Data Generation/Receive State.
 - 6'h12: Clock Extension State.
 - 6'h13: Halt State.

RO

0x0

15:14

Reserved_4

Reserved bitfield added by Magillem

RO

0x0

13:8

CM_TFR_STS

Transfer Type Status

Indicates the type of transfer currently executing by the DWC_mipi_i3c controller.


In Master mode of operation:
 - 6'h0: IDLE (Controller is in Idle state, waiting for commands from application or Slave initated In-band Interrupt)
 - 6'h1: Broadcast CCC Write Transfer.
 - 6'h2: Directed CCC Write Transfer.
 - 6'h3: Directed CCC Read Transfer.
 - 6'h4: ENTDAA Address Assignment Transfer.
 - 6'h5: SETDASA Address Assignment Transfer.
 - 6'h6: Private I3C SDR Write Transfer.
 - 6'h7: Private I3C SDR Read Transfer.
 - 6'h8: Private I2C SDR Write Transfer.
 - 6'h9: Private I2C SDR Read Transfer.
 - 6'hA: Private HDR Ternary Symbol(TS) Write Transfer.
 - 6'hB: Private HDR Ternary Symbol(TS) Read Transfer.
 - 6'hC: Private HDR Double-Data Rate(DDR) Write Transfer.
 - 6'hD: Private HDR Double-Data Rate(DDR) Read Transfer.
 - 6'hE: Servicing In-Band Interrupt Transfer.
 - 6'hF: Halt state (Controller is in Halt State, waiting for the application to resume through DEVICE_CTRL Register)

RO

0x0

7:3

Reserved_3

Reserved bitfield added by Magillem

RO

0x0

CURRENT_MASTER

This Bit is used to check whether the Master is Current Master or not. The Current Master is the Master
that owns the SCL line.

If this bit is set to 0, the Master is not Current Master and requires to request and the ownership
before initiating any transfer on the line.

If this bit is set to 1, the Master is the Current Master and can initate the transfers on the line.
 - 0: Master is not Current Master
 - 1: Master is Current Master

Value	Description
0x0	Master is not a Current Master
0x1	Master is Current Master

RO

0x0

SDA_LINE_SIGNAL_LEVEL

This bit is used to check the SDA line level to recover from errors and for debugging. This bit
reflects the value of synchronized sda_in_a signal. This is valid in Master mode only.

RO

0x1

SCL_LINE_SIGNAL_LEVEL

This bit is used to check the SCL line level to recover from errors and for debugging. This bit
reflects the value of synchronized scl_in_a signal. This is valid in Master mode only

RO

0x1