INTR_FORCE

         
Interrupt Force Enable Register

Individual interrupts can be forcefully triggered if corresponding Force Enable bit is set, provided
the corresponding bit in the INTR_STATUS_EN register is set.


Module Instance	Base Address	Register Address
`i_i3c_main_master__i3c_m_apb_slv__10da0000__DWC_mipi_i3c_block__SEG_L4_SP_i3c0_0x0_0x1000`	`0x10DA0000`	`0x10DA0048`

Size: 32

Offset: 0x48

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_7` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_7` `WO 0x0`						`TRANSFER_ERR_FORCE_EN` `WO 0x0`	`Reserved_6` `WO 0x0`			`TRANSFER_ABORT_FORCE_EN` `WO 0x0`	`RESP_READY_FORCE_EN` `WO 0x0`	`CMD_QUEUE_READY_FORCE_EN` `WO 0x0`	`IBI_THLD_FORCE_EN` `WO 0x0`	`RX_THLD_FORCE_EN` `WO 0x0`	`TX_THLD_FORCE_EN` `WO 0x0`

INTR_FORCE Fields


Bit	Name	Description	Access	Reset
31:10	`Reserved_7`	Reserved bitfield added by Magillem	`WO`	`0x0`
9	`TRANSFER_ERR_FORCE_EN`	Transfer Error Force Enable	`WO`	`0x0`
8:6	`Reserved_6`	Reserved bitfield added by Magillem	`WO`	`0x0`
5	`TRANSFER_ABORT_FORCE_EN`	Transfer Abort Force Enable This field is used in master mode of operation.	`WO`	`0x0`
4	`RESP_READY_FORCE_EN`	Response Queue Ready Force Enable	`WO`	`0x0`
3	`CMD_QUEUE_READY_FORCE_EN`	Command Queue Ready Force Enable	`WO`	`0x0`
2	`IBI_THLD_FORCE_EN`	IBI Buffer Threshold Force Enable This field is used in master mode of operation.	`WO`	`0x0`
1	`RX_THLD_FORCE_EN`	Receive Buffer Threshold Force Enable	`WO`	`0x0`
0	`TX_THLD_FORCE_EN`	Transmit Buffer Threshold Force Enable	`WO`	`0x0`