DEVICE_ADDR 

         

In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit.
Module Instance Base Address Register Address
i_i3c_main_master__i3c_m_apb_slv__10da0000__DWC_mipi_i3c_block__SEG_L4_SP_i3c0_0x0_0x1000 0x10DA0000 0x10DA0004

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DYNAMIC_ADDR_VALID

RW 0x1

Reserved_1

RO 0x0

DYNAMIC_ADDR

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_0

RO 0x0

DEVICE_ADDR Fields

Bit Name Description Access Reset
31 DYNAMIC_ADDR_VALID 
Dynamic Address Valid

This bit is used to control whether the DYNAMIC_ADDR is valid or not.

 - In I3C Main Master mode, the user sets this bit to 1 as it self-assigns its dynamic address.
 - In all other operation modes, the Controller sets this bit to 1 when Main Master assigns the Dynamic address during ENTDAA or SETDASA mechanism.
Value Description
0x0 Dynamic Address is invalid
0x1 Dynamic Address is valid
RW 0x1
30:23 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
22:16 DYNAMIC_ADDR 
Device Dynamic Address.

This field is used to program the Device Dynamic Address. The Controller uses this address for I3C transfers.

 - In Main Master mode, the user/application has to program the Dynamic Address through the Slave interface as it self-assigns its Dynamic Address.
 - In all other modes, the Main Master assigns this address during ENTDAA or SETDASA mechanism.
RW 0x0
15:0 Reserved_0 
Reserved bitfield added by Magillem
 RO 0x0