DEVICE_CTRL
DWC_mipi_i3c control Register
This Register controls the transfer properties and disposition of controller's capabilities.
| Module Instance | Base Address | Register Address |
|---|---|---|
i_i3c_main_master__i3c_m_apb_slv__10da0000__DWC_mipi_i3c_block__SEG_L4_SP_i3c0_0x0_0x1000
|
0x10DA0000
|
0x10DA0000
|
Size: 32
Offset: 0x
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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DEVICE_CTRL Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 |
ENABLE
|
Controls whether or not DWC_mipi_i3c is enabled. - 1: Enables the DWC_mipi_i3c controller. - 0: Disables the DWC_mipi_i3c controller. In Master mode of operation, software can disable DWC_mipi_i3c while it is active. However, the controller may not get disabled immediately and is 'Disabled' after commands in the Command queue (if any) are executed leading to a STOP condition on the bus and Master FSM is in IDLE state (as indicated by PRESENT_STATE Register). |
RW
|
0x0
|
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| 30 |
RESUME
|
DWC_mipi_i3c Resume This bit is used to resume the controller after it goes to the halt state. In the Master mode of operation, the controller goes to the halt state (as indicated in PRESENT_STATE Register) due to any type of error in the transfer (the type of error is indicated by ERR_STATUS field in the RESPONSE_QUEUE_PORT register). After the controller gones to the halt state, the application has to write 1'b1 to this bit to resume the controller. This bit is auto-cleared once the controller resumes the transfers by initiating the next command. |
RW
|
0x0
|
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| 29 |
ABORT
|
DWC_mipi_i3c Abort This bit is used in Master mode of operation. This bit allows the controller to relinquish the DWC_mipi_i3c bus before completing the issued transfer. In response to an ABORT request, the controller issues the STOP condition after the complete data byte is transferred or received. This bit is auto-cleared once the transfer is aborted and the controller issues a 'Transfer Abort' interrupt. |
RW
|
0x0
|
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| 28 |
DMA_ENABLE
|
DMA Handshake Interface Enable This bit is used to enable or disable the DMA Handshaking interface, and is applicable to both Master and Slave modes of operation. - 1: Enables the DMA handshake control to interact with external DMA. - 0: The DMA handshake control has no significance. |
RW
|
0x0
|
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| 27:9 |
Reserved_3
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
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| 8 |
HOT_JOIN_CTRL
|
Hot-Join ACK/NACK Control This bit is used in master mode of operation. This bit acts as a global control to ACK/NACK the Hot-Join request from the devices. The DWC_mipi_i3c Master ACK/NACKs the Hot-Join request from other devices connected on the DWC_mipi_i3c bus, based on programming of this bit. - 0: ACK the Hot-join request. - 1: NACK and send broadcast CCC to disable Hot-Join.
|
RW
|
0x0
|
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| 7 |
I2C_SLAVE_PRESENT
|
I2C Slave Present This bit is used in master mode of operation. This bit indicates whether any Legacy I2C devices are present in the system. In HDR mode, this field is used to select TSL over TSP in a mixed bus configuration.
|
RW
|
0x0
|
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| 6:1 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
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| 0 |
IBA_INCLUDE
|
I3C Broadcast Address include This bit is used in Master mode of operation. This bit is used to include DWC_mipi_i3c broadcast address (0x7E) for private transfer. Note: If DWC_mipi_i3c broadcast address is not included for the private transfers, In-band Interrupts (IBI) driven from Slaves might not win address arbitration. Hence, the IBIs get delayed.
|
RW
|
0x0
|