FPGA2SOC Summary

Base Address: 0x1C001000


Register Address Offset	Bit Fields
`i_ccu__DSU__1c000000__FPGA2SOC`
`XAIUIDR` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`	`NUnitId` `RO 0x1`			`NRRI` `RO 0x0`				`RPN` `RO 0x1`
`XAIUFUIDR` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`												`FUnitId` `RO 0x1`
`XAIUTCR` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd4` `RO 0x0`												`TransOrderModeWr` `RW 0x2`		`TransOrderModeRd` `RW 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd3` `RO 0x0`						`SysCoAttach` `RW 0x0`	`SysCoDisable` `RW 0x0`	`Rsvd2` `RO 0x0`			`EventDisable` `RW 0x0`	`Rsvd1` `RO 0x0`
`XAIUTAR` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`									`SysCoError` `RO 0x0`	`SysCoAttached` `RO 0x0`	`SysCoConnecting` `RO 0x0`	`Rsvd1` `RO 0x0`			`TransActv` `RO 0x0`
`XAIUUEDR` `0x256` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`											`TimeoutErrDetEn` `RW 0x0`	`DecErrDetEn` `RW 0x0`	`MemErrDetEn` `RW 0x0`	`TransErrDetEn` `RW 0x0`	`ProtErrDetEn` `RW 0x0`
`XAIUUEIR` `0x260` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`											`TimeoutErrIntEn` `RW 0x0`	`DecErrIntEn` `RW 0x0`	`MemErrIntEn` `RW 0x0`	`TransErrIntEn` `RW 0x0`	`ProtErrIntEn` `RW 0x0`
`XAIUUESR` `0x264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`XAIUUELR0` `0x268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`XAIUUELR1` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`												`ErrAddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrAddr` `RW 0x0`
`XAIUUESAR` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RW 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`XAIUCECR` `0x320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`				`ErrThreshold` `RW 0x0`								`Rsvd1` `RO 0x0`		`ErrIntEn` `RW 0x0`	`ErrDetEn` `RW 0x0`
`XAIUCESR` `0x324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`		`ErrCount` `RO 0x0`								`ErrCountOverflow` `RO 0x0`	`ErrVld` `RW 0x0`
`XAIUCELR0` `0x328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`XAIUCELR1` `0x332` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`												`ErrAddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrAddr` `RW 0x0`
`XAIUCESAR` `0x336` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RW 0x0`				`Rsvd1` `RO 0x0`		`ErrCount` `RW 0x0`								`ErrCountOverflow` `RW 0x0`	`ErrVld` `RW 0x0`
`XAIUCRTR` `0x380` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`ResThreshold` `RW 0x1`
`XAIUTOCR` `0x400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TimeOutRefEn` `RW 0x0`	`TimeOutThreshold` `RW 0x4000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TimeOutThreshold` `RW 0x4000`
`XAIUQOSCR` `0x512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EventThreshold` `RW 0x40`
`XAIUQOSSR` `0x516` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`												`EventStatusCount` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EventStatusCount` `RW 0x0`												`Rsvd1` `RO 0x0`		`EventStatusCountOverflow` `RW 0x0`	`EventStatus` `RO 0x0`
`XAIUNRSBAR` `0x896` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NRSBA` `RO 0x1C0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NRSBA` `RO 0x1C0`
`XAIUNRSBHR` `0x900` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NRSBA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NRSBA` `RW 0x0`
`XAIUNRSBLR` `0x904` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BALoaded` `RO 0x0`	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`NRSDIIId` `RO 0x4`										`Rsvd1` `RO 0x0`
`XAIUBRAR` `0x928` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x1`	`HUT` `RW 0x1`	`Rsvd3` `RO 0x0`					`Size` `RW 0x7`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x3`					`Rsvd1` `RO 0x0`
`XAIUBRBLR` `0x932` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUBRBHR` `0x936` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUAMIGR` `0x960` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`											`AMIGS` `RW 0x0`				`Valid` `RW 0x0`
`XAIUMIFSR` `0x964` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd5` `RO 0x0`					`MIG16AIFId` `RW 0x0`			`Rsvd4` `RO 0x0`					`MIG8AIFId` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd3` `RO 0x0`					`MIG4AIFId` `RW 0x0`			`Rsvd2` `RO 0x0`	`MIG3AIFId` `RW 0x0`			`Rsvd1` `RO 0x0`	`MIG2AIFId` `RW 0x0`
`XAIUGPRAR0` `0x1024` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR0` `0x1028` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR0` `0x1032` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR1` `0x1040` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR1` `0x1044` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR1` `0x1048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR2` `0x1056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR2` `0x1060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR2` `0x1064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR3` `0x1072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR3` `0x1076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR3` `0x1080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR4` `0x1088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR4` `0x1092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR4` `0x1096` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR5` `0x1104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR5` `0x1108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR5` `0x1112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR6` `0x1120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR6` `0x1124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR6` `0x1128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR7` `0x1136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR7` `0x1140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR7` `0x1144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR8` `0x1152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR8` `0x1156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR8` `0x1160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR9` `0x1168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR9` `0x1172` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR9` `0x1176` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR10` `0x1184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR10` `0x1188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR10` `0x1192` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUGPRAR11` `0x1200` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`XAIUGPRBLR11` `0x1204` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`XAIUGPRBHR11` `0x1208` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`XAIUTBALR0` `0x2056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`base_addr_lo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`base_addr_lo` `RW 0x0`
`XAIUTBAHR0` `0x2060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`base_addr_hi` `RW 0x0`
`XAIUTOPCR00` `0x2064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`valid2` `RW 0x0`	`opcode2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`valid1` `RW 0x0`	`opcode1` `RW 0x0`
`XAIUTOPCR10` `0x2068` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`valid4` `RW 0x0`	`opcode4` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`valid3` `RW 0x0`	`opcode3` `RW 0x0`
`XAIUTUBR0` `0x2072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`user` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`user` `RW 0x0`
`XAIUTUBMR0` `0x2076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`user_mask` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`user_mask` `RW 0x0`
`XAIUCCTRLR` `0x2304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`inc` `RW 0x100`												`gain` `RW 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd` `RO 0x0`								`dn0Rx` `RW 0x0`	`dn0Tx` `RW 0x0`	`ndn2Rx` `RW 0x0`	`ndn2Tx` `RW 0x0`	`ndn1Rx` `RW 0x0`	`ndn1Tx` `RW 0x0`	`ndn0Rx` `RW 0x0`	`ndn0Tx` `RW 0x0`
`XAIUTCTRLR0` `0x2308` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`memattr` `RW 0x0`				`ar` `RW 0x0`	`aw` `RW 0x0`	`Rsvd2` `RO 0x0`		`range` `RW 0x0`					`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`				`hui` `RW 0x0`					`hut` `RW 0x0`	`target_type_match_en` `RW 0x0`	`user_match_en` `RW 0x0`	`memattr_match_en` `RW 0x0`	`opcode_match_en` `RW 0x0`	`addr_match_en` `RW 0x0`	`native_trace_en` `RW 0x1`
`XAIUEDR0` `0x2560` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MRW` `RW 0x0`								`MRR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MRU` `RW 0x0`								`MRC` `RW 0x0`
`XAIUEDR1` `0x2564` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cfg` `RW 0x8`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cfg` `RW 0x8`
`XAIUEDR2` `0x2568` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`								`RD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`WR` `RW 0x0`
`XAIUEDR3` `0x2572` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`								`STT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`OTT` `RW 0x0`
`XAIUEDR4` `0x2576` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`								`RD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`WR` `RW 0x0`
`XAIUEDR5` `0x2580` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`EV` `RW 0x0`
`XAIUEDR6` `0x2584` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`												`QOS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DVE` `RW 0x0`				`DII` `RW 0x0`				`DMI` `RW 0x0`				`DCE` `RW 0x0`
`XAIUEDR7` `0x2588` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIME` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIME` `RW 0x0`				`EVENT` `RW 0x0`
`XAIUCNTCR0` `0x2816` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`XAIUCNTVR0` `0x2820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`XAIUCNTSR0` `0x2824` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`XAIUCNTCR1` `0x2832` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`XAIUCNTVR1` `0x2836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`XAIUCNTSR1` `0x2840` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`XAIUCNTCR2` `0x2848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`XAIUCNTVR2` `0x2852` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`XAIUCNTSR2` `0x2856` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`XAIUCNTCR3` `0x2864` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`XAIUCNTVR3` `0x2868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`XAIUCNTSR3` `0x2872` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`XAIUNRSAR` `0x4080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`															`NRSAR` `RW 0x1`
`XAIUENGIDR` `0x4084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`EngVerId` `RO 0xB92A000B`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EngVerId` `RO 0xB92A000B`
`XAIUINFOR` `0x4092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`											`UST` `RO 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UT` `RO 0x1`				`ImplVer` `RO 0x323`