XAIUEDR6 

         Credit adjustment per target type basis: 0x1: Max 1. 0x2: Max 2. 0x3: Max 3. 0x5: Minus 1. 0x6: Minus 2. 0x7: Minus 3. 0x9: 1 read others writes. 0xa: Reserve 1 write. 0xb: No limit. 0xd: reserve 1 extra write, 0xe: reserve 2 extra writes, 0xf: reserve 3 extra writes, Others: no change
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__FPGA2SOC 0x1C001000 0x1C001A18

Size: 32

Offset: 0xA18

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Rsvd1

RO 0x0

QOS

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DVE

RW 0x0

DII

RW 0x0

DMI

RW 0x0

DCE

RW 0x0

XAIUEDR6 Fields

Bit Name Description Access Reset
31:20 Rsvd1 
Reserved
 RO 0x0
19:16 QOS 
QOS credit adjustment.
 RW 0x0
15:12 DVE 
DVE credit adjustment.
 RW 0x0
11:8 DII 
DII credit adjustment.
 RW 0x0
7:4 DMI 
DMI credit adjustment.
 RW 0x0
3:0 DCE 
DCE credit adjustment.
 RW 0x0