XAIUTAR

         Transaction Activity Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__FPGA2SOC`	`0x1C001000`	`0x1C001044`

Size: 32

Offset: 0x44

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd2` `RO 0x0`									`SysCoError` `RO 0x0`	`SysCoAttached` `RO 0x0`	`SysCoConnecting` `RO 0x0`	`Rsvd1` `RO 0x0`			`TransActv` `RO 0x0`

XAIUTAR Fields


Bit	Name	Description	Access	Reset
31:7	`Rsvd2`	Reserved	`RO`	`0x0`
6	`SysCoError`	1 indicates Error was detected during previous or current SysCo event. This bit clears itself when the SysCo process triggers next time.	`RO`	`0x0`
5	`SysCoAttached`	1 indicates that SysCo is Attached; 0 indicates it is detached.	`RO`	`0x0`
4	`SysCoConnecting`	1 indicates that SysCo is in the process of connecting.	`RO`	`0x0`
3:1	`Rsvd1`	Reserved	`RO`	`0x0`
0	`TransActv`	This bit is set when there is one or more active transactions inside the Unit.	`RO`	`0x0`