XAIUEDR0

         Credit on a per message type basis.


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__FPGA2SOC`	`0x1C001000`	`0x1C001A00`

Size: 32

Offset: 0xA00

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`MRW` `RW 0x0`								`MRR` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`MRU` `RW 0x0`								`MRC` `RW 0x0`

XAIUEDR0 Fields


Bit	Name	Description	Access	Reset
31:24	`MRW`	DTW credit.	`RW`	`0x0`
23:16	`MRR`	DTR credit.	`RW`	`0x0`
15:8	`MRU`	Update credit.	`RW`	`0x0`
7:0	`MRC`	Command credit.	`RW`	`0x0`