XAIUMIFSR 

         Memory Interleave Function Select Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__FPGA2SOC 0x1C001000 0x1C0013C4

Size: 32

Offset: 0x3C4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Rsvd5

RO 0x0

MIG16AIFId

RW 0x0

Rsvd4

RO 0x0

MIG8AIFId

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rsvd3

RO 0x0

MIG4AIFId

RW 0x0

Rsvd2

RO 0x0

MIG3AIFId

RW 0x0

Rsvd1

RO 0x0

MIG2AIFId

RW 0x0

XAIUMIFSR Fields

Bit Name Description Access Reset
31:27 Rsvd5 
Reserved
 RO 0x0
26:24 MIG16AIFId 
Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS
 RW 0x0
23:19 Rsvd4 
Reserved
 RO 0x0
18:16 MIG8AIFId 
Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS
 RW 0x0
15:11 Rsvd3 
Reserved
 RO 0x0
10:8 MIG4AIFId 
Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS
 RW 0x0
7 Rsvd2 
Reserved
 RO 0x0
6:4 MIG3AIFId 
Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS
 RW 0x0
3 Rsvd1 
Reserved
 RO 0x0
2:0 MIG2AIFId 
Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS
 RW 0x0