DWC_usb31_block_debug Address Map

USB 3.1 Debug Register Block
Module Instance Base Address End Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_debug__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D800 0x1100D9FF
Register Group Offset
RHBDBG_REGS 0
Register Offset Width Access Reset Value Description
BRAMHIADDR 0x4C 32 RW 0x00000000 
RAM HIGHER ADDRESS REGISTER
BRSERRCNT 0x50 32 RW 0x00000000 
RAM Single Error Count. 6 bit count for each od 5 RAMS
BRMERRCNT 0x54 32 RW 0x00000000 
RAM Multiple Error Count. 6 bit count for each od 5 RAMS
BRAMECCERR 0x58 32 RW 0x00000000 
RAM ECC Error Register
BRERRCTL 0x5C 32 RW 0x00000000 
RAM ERROR CONTROL REGISTER
BRAM0ADDRERR 0x60 32 RW 0x00000000 
Address of RAM0 which had uncorrectable error
BRAM1ADDRERR 0x64 32 RW 0x00000000 
RAM1 Address Error Register
BRAM2ADDRERR 0x68 32 RW 0x00000000 
RAM2 Address Error Register
BRAM3ADDRERR 0x6C 32 RW 0x00000000 
RAM3 Address Error Register
BRAM4ADDRERR 0x70 32 RW 0x00000000 
RAM4 Address Error Register
BLOOPBCKCTRL 0x100 32 RW 0x00000000 
Loopback Control Register
BLOOPBCKTFERSZ 0x104 32 RW 0x00000000 
Loopback Transfer Size Register
BBISTDATAPATSEED 0x108 32 RW 0x00000000 
BIST Data Pattern Seed Register
   - Used only in BIST MODE
BBISTCTRL 0x10C 32 RW 0x00000000 
BIST Control Register
   - Used only in BIST MODE
BBISTXFERSTS0 0x110 32 RO 0x00000000 
BIST Transfer Status Register 0 
  
   Note : BIST Transfer Status contains 4 DWORD distributed over four 32 bit register BBISTXFERSTS0,BBISTXFERSTS1,BBISTXFERSTS2,BBISTXFERSTS3
BBISTXFERSTS1 0x114 32 RO 0x00000000 
BIST Transfer Status Register 1 
  
   Note : BIST Transfer Status contains 4 DWORD distributed over four 32 bit register BBISTXFERSTS0,BBISTXFERSTS1,BBISTXFERSTS2,BBISTXFERSTS3
BBISTXFERSTS2 0x118 32 RO 0x00000000 
BIST Transfer Status Register 2 
  
   Note : BIST Transfer Status contains 4 DWORD distributed over four 32 bit register BBISTXFERSTS0,BBISTXFERSTS1,BBISTXFERSTS2,BBISTXFERSTS3
BBISTXFERSTS3 0x11C 32 RO 0x00000000 
BIST Transfer Status Register 3 
  
   Note : BIST Transfer Status contains 4 DWORD distributed over four 32 bit register BBISTXFERSTS0,BBISTXFERSTS1,BBISTXFERSTS2,BBISTXFERSTS3
BBISTEXPDATASTS0 0x120 32 RO 0x00000000 
BIST Expected Data Status Register 0
  
   Note : BIST Expected Data Status indicates the expected data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTEXPDATASTS0,BBISTEXPDATASTS1,BBISTEXPDATASTS2,BBISTEXPDATASTS3 
  
   - Only Expected Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.
BBISTEXPDATASTS1 0x124 32 RO 0x00000000 
BIST Expected Data Status Register 1
  
   Note : BIST Expected Data Status indicates the expected data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTEXPDATASTS0,BBISTEXPDATASTS1,BBISTEXPDATASTS2,BBISTEXPDATASTS3 
  
   - Only Expected Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.
BBISTEXPDATASTS2 0x128 32 RO 0x00000000 
BIST Expected Data Status Register 2
  
   Note : BIST Expected Data Status indicates the expected data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTEXPDATASTS0,BBISTEXPDATASTS1,BBISTEXPDATASTS2,BBISTEXPDATASTS3 
  
   - Only Expected Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.
BBISTEXPDATASTS3 0x12C 32 RO 0x00000000 
BIST Expected Data Status Register 3
  
   Note : BIST Expected Data Status indicates the expected data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTEXPDATASTS0,BBISTEXPDATASTS1,BBISTEXPDATASTS2,BBISTEXPDATASTS3 
  
   - Only Expected Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.
BBISTRCVDDATASTS0 0x130 32 RO 0x00000000 
BIST Received Data Status Register 0
  
   Note : BIST Received Data Status indicates the received data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTRCVDDATASTS0,BBISTRCVDDATASTS1,BBISTRCVDDATASTS2,BBISTRCVDDATASTS3
  
   - Only Received Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.
BBISTRCVDDATASTS1 0x134 32 RO 0x00000000 
BIST Received Data Status Register 1
  
   Note : BIST Received Data Status indicates the received data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTRCVDDATASTS0,BBISTRCVDDATASTS1,BBISTRCVDDATASTS2,BBISTRCVDDATASTS3
  
   - Only Received Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.
BBISTRCVDDATASTS2 0x138 32 RO 0x00000000 
BIST Received Data Status Register 2
  
   Note : BIST Received Data Status indicates the received data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTRCVDDATASTS0,BBISTRCVDDATASTS1,BBISTRCVDDATASTS2,BBISTRCVDDATASTS3
  
   - Only Received Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.
BBISTRCVDDATASTS3 0x13C 32 RO 0x00000000 
BIST Received Data Status Register 3
  
   Note : BIST Received Data Status indicates the received data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTRCVDDATASTS0,BBISTRCVDDATASTS1,BBISTRCVDDATASTS2,BBISTRCVDDATASTS3
  
   - Only Received Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.