BRSERRCNT

         RAM Single Error Count. 6 bit count for each od 5 RAMS


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_debug__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D800`	`0x1100D850`

Size: 32

Offset: 0x50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`		`ram4serrcnt` `RW 0x0`						`ram3serrcnt` `RW 0x0`						`ram2serrcnt` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ram2serrcnt` `RW 0x0`				`ram1serrcnt` `RW 0x0`						`ram0serrcnt` `RW 0x0`

BRSERRCNT Fields


Bit	Name	Description	Access	Reset
31:30	`Reserved_1`	Reserved_1	`RO`	`0x0`
29:24	`ram4serrcnt`	RAM4 Single Error Count	`RW`	`0x0`
23:18	`ram3serrcnt`	RAM3 Single Error Count	`RW`	`0x0`
17:12	`ram2serrcnt`	RAM2 Single Error Count	`RW`	`0x0`
11:6	`ram1serrcnt`	RAM1 Single Error Count	`RW`	`0x0`
5:0	`ram0serrcnt`	RAM0 Single Error Count	`RW`	`0x0`