BBISTCTRL 

         BIST Control Register
   - Used only in BIST MODE
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_debug__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D800 0x1100D90C

Size: 32

Offset: 0x10C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

start_BIST_test

RW 0x0

BIST_test_type

RW 0x0

fail

RW 0x0

reserved_28_27

RW 0x0

BIST_pattern

RW 0x0

BIST_iteration_cnt

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIST_iteration_cnt

RW 0x0

BBISTCTRL Fields

Bit Name Description Access Reset
31 start_BIST_test 
Start BIST Test
   - 1'b0 : Stop Test
   - 1'b1 : Start Test
  This bit is cleared when the test is completed.
 RW 0x0
30 BIST_test_type 
BIST Test Type
   - 1'b0 : BIST Transfer loopback test
   - 1'b1 : BIST Register/RAM test
 RW 0x0
29 fail 
fail
 RW 0x0
28:27 reserved_28_27 
Reserved
 RW 0x0
26:24 BIST_pattern 
BIST Pattern
   - 3'b000: Use same pattern
   - 3'b001: Alternate Invert (If start will AA, then it will perform AA/55 BIST pattern) 
   - 3'b010: Increment Pattern
   - 3'b011: LSFR
   - 3'b100: Shift right (Walking 1 and Walking 0 testing)
   - others: Reserved
 RW 0x0
23:0 BIST_iteration_cnt 
BIST Iteration Count 
   - 0: Continuous till stop/fail
   - x(others): Iteration till count x stop/fail
 RW 0x0