BRAMHIADDR

         RAM HIGHER ADDRESS REGISTER


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_debug__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D800`	`0x1100D84C`

Size: 32

Offset: 0x4C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_2` `RO 0x0`											`ram_select` `RW 0x0`			`ramhiaddr` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ramhiaddr` `RW 0x0`				`Reserved_1` `RO 0x0`

BRAMHIADDR Fields


Bit	Name	Description	Access	Reset
31:21	`Reserved_2`	Reserved_2	`RO`	`0x0`
20:18	`ram_select`	Chip select for RAM 0-4	`RW`	`0x0`
17:12	`ramhiaddr`	Partial decoding bits for RAM higher address	`RW`	`0x0`
11:0	`Reserved_1`	Reserved_1	`RO`	`0x0`