BBISTRCVDDATASTS2

         BIST Received Data Status Register 2
  
   Note : BIST Received Data Status indicates the received data when BIST fails which is contained in 4 DWORD distributed over four 32 bit register BBISTRCVDDATASTS0,BBISTRCVDDATASTS1,BBISTRCVDDATASTS2,BBISTRCVDDATASTS3
  
   - Only Received Data [DWC_USB31_MDWIDTH-1:0] is valid, other bits are don't care if any.


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_debug__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D800`	`0x1100D938`

Size: 32

Offset: 0x138

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`received_data` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`received_data` `RO 0x0`

BBISTRCVDDATASTS2 Fields


Bit	Name	Description	Access	Reset
31:0	`received_data`	Received Data-2	`RO`	`0x0`