DWC_usb31_block_debug Summary

USB 3.1 Debug Register Block

Base Address: 0x1100D800


Register Address Offset	Bit Fields
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_debug__SEG_L4_AHB_USB1_0x0_0x100000`
`BRAMHIADDR` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`											`ram_select` `RW 0x0`			`ramhiaddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ramhiaddr` `RW 0x0`				`Reserved_1` `RO 0x0`
`BRSERRCNT` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`		`ram4serrcnt` `RW 0x0`						`ram3serrcnt` `RW 0x0`						`ram2serrcnt` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ram2serrcnt` `RW 0x0`				`ram1serrcnt` `RW 0x0`						`ram0serrcnt` `RW 0x0`
`BRMERRCNT` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`		`ram4merrcnt` `RW 0x0`						`ram3merrcnt` `RW 0x0`						`ram2merrcnt` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ram2merrcnt` `RW 0x0`				`ram1merrcnt` `RW 0x0`						`ram0merrcnt` `RW 0x0`
`BRAMECCERR` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`reserved_31_12` `RO 0x0`				`ramserr` `RW 0x0`	`rammerr` `RW 0x0`	`ramserrvec` `RW 0x0`					`rammerrvec` `RW 0x0`
`BRERRCTL` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`														`rserrclr` `RW 0x0`	`rmerrclr` `RW 0x0`
`BRAM0ADDRERR` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ram0errloc` `RO 0x0`
`BRAM1ADDRERR` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ram1errloc` `RO 0x0`
`BRAM2ADDRERR` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ram2errloc` `RO 0x0`
`BRAM3ADDRERR` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ram3errloc` `RO 0x0`
`BRAM4ADDRERR` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ram4errloc` `RO 0x0`
`BLOOPBCKCTRL` `0x256` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_11` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`reserved_31_11` `RO 0x0`					`reserved_10_8` `RW 0x0`			`loopback_prtnum` `RW 0x0`				`loopback_level` `RW 0x0`		`loopback_mode` `RW 0x0`	`loopback_mode_en` `RW 0x0`
`BLOOPBCKTFERSZ` `0x260` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_24` `RO 0x0`								`loopback_xfer_sz` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`loopback_xfer_sz` `RW 0x0`
`BBISTDATAPATSEED` `0x264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BIST_pattern_seed` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BIST_pattern_seed` `RW 0x0`
`BBISTCTRL` `0x268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`start_BIST_test` `RW 0x0`	`BIST_test_type` `RW 0x0`	`fail` `RW 0x0`	`reserved_28_27` `RW 0x0`		`BIST_pattern` `RW 0x0`			`BIST_iteration_cnt` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BIST_iteration_cnt` `RW 0x0`
`BBISTXFERSTS0` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_24` `RO 0x0`								`bist_pending_trans_size` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`bist_pending_trans_size` `RO 0x0`
`BBISTXFERSTS1` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_24` `RO 0x0`								`failed_pending_trans_size` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`failed_pending_trans_size` `RO 0x0`
`BBISTXFERSTS2` `0x280` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_24` `RO 0x0`								`failed_iteration` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`failed_iteration` `RO 0x0`
`BBISTXFERSTS3` `0x284` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`reserved_31_4` `RO 0x0`												`loopback_statemachine` `RO 0x0`
`BBISTEXPDATASTS0` `0x288` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`exp_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`exp_data` `RO 0x0`
`BBISTEXPDATASTS1` `0x292` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`exp_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`exp_data` `RO 0x0`
`BBISTEXPDATASTS2` `0x296` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`exp_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`exp_data` `RO 0x0`
`BBISTEXPDATASTS3` `0x300` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`exp_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`exp_data` `RO 0x0`
`BBISTRCVDDATASTS0` `0x304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`received_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`received_data` `RO 0x0`
`BBISTRCVDDATASTS1` `0x308` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`received_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`received_data` `RO 0x0`
`BBISTRCVDDATASTS2` `0x312` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`received_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`received_data` `RO 0x0`
`BBISTRCVDDATASTS3` `0x316` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`received_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`received_data` `RO 0x0`