CCU_DMI0 Summary

Base Address: 0x1C007000


Register Address Offset	Bit Fields
`i_ccu__DSU__1c000000__CCU_DMI0`
`DMIUIDR` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`	`NUnitId` `RO 0x0`			`NRRI` `RO 0x0`				`RPN` `RO 0x7`
`DMIUFUIDR` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`												`FUnitId` `RO 0x7`
`DMIUTAR` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`															`TransActv` `RO 0x0`
`DMIUUEDR` `0x256` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`											`TimeoutErrDetEn` `RW 0x0`	`Rsvd1` `RO 0x0`	`MemErrDetEn` `RW 0x0`	`TransErrDetEn` `RW 0x0`	`ProtErrDetEn` `RW 0x0`
`DMIUUEIR` `0x260` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`											`TimeoutErrIntEn` `RW 0x0`	`Rsvd1` `RO 0x0`	`MemErrIntEn` `RW 0x0`	`TransErrIntEn` `RW 0x0`	`ProtErrIntEn` `RW 0x0`
`DMIUUESR` `0x264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`DMIUUELR0` `0x268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`DMIUUELR1` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`												`ErrAddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrAddr` `RW 0x0`
`DMIUUESAR` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RW 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`DMIUCECR` `0x320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`				`ErrThreshold` `RW 0x0`								`Rsvd1` `RO 0x0`		`ErrIntEn` `RW 0x0`	`ErrDetEn` `RW 0x0`
`DMIUCESR` `0x324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`		`ErrCount` `RO 0x0`								`ErrCountOverflow` `RO 0x0`	`ErrVld` `RW 0x0`
`DMIUCELR0` `0x328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`DMIUCELR1` `0x332` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`												`ErrAddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrAddr` `RW 0x0`
`DMIUCESAR` `0x336` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RW 0x0`				`Rsvd1` `RO 0x0`		`ErrCount` `RW 0x0`								`ErrCountOverflow` `RW 0x0`	`ErrVld` `RW 0x0`
`DMIUTOCR` `0x400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TimeOutRefEn` `RW 0x0`	`TimeOutThreshold` `RW 0x4000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TimeOutThreshold` `RW 0x4000`
`DMIUQOSCR0` `0x512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EventThreshold` `RW 0x40`
`DMIUSMCTCR` `0x768` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`														`AllocEn` `RW 0x0`	`LookupEn` `RW 0x0`
`DMIUSMCTAR` `0x772` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`														`AllocActive` `RO 0x0`	`EvictActive` `RO 0x0`
`DMIUSMCAPR` `0x776` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`											`WrAllocDisable` `RW 0x0`	`RdAllocDisable` `RW 0x0`	`DtyWrAllocDisable` `RW 0x0`	`ClnWrAllocDisable` `RW 0x0`	`TOFAllocDisable` `RW 0x0`
`DMIUSMCISR` `0x780` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`														`DataInitDone` `RO 0x0`	`TagInitDone` `RO 0x0`
`DMIUSMCMCR` `0x832` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`									`SecAttr` `RW 0x0`	`ArrayID` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`												`MntOp` `RW 0x0`
`DMIUSMCMAR` `0x836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`															`MntOpActv` `RO 0x0`
`DMIUSMCMLR0` `0x840` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MntWord` `RW 0x0`						`MntWay` `RW 0x0`						`MntSet` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MntSet` `RW 0x0`
`DMIUSMCMLR1` `0x844` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MntRange` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MntAddr` `RW 0x0`
`DMIUSMCMDR` `0x848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MntData` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MntData` `RW 0x0`
`DMICCTRLR` `0x2048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`inc` `RW 0x100`												`gain` `RW 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd` `RO 0x0`								`dn0Rx` `RW 0x0`	`dn0Tx` `RW 0x0`	`ndn2Rx` `RW 0x0`	`ndn2Tx` `RW 0x0`	`ndn1Rx` `RW 0x0`	`ndn1Tx` `RW 0x0`	`ndn0Rx` `RW 0x0`	`ndn0Tx` `RW 0x0`
`DMICNTCR0` `0x2816` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DMICNTVR0` `0x2820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DMICNTSR0` `0x2824` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DMICNTCR1` `0x2832` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DMICNTVR1` `0x2836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DMICNTSR1` `0x2840` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DMICNTCR2` `0x2848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DMICNTVR2` `0x2852` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DMICNTSR2` `0x2856` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DMICNTCR3` `0x2864` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DMICNTVR3` `0x2868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DMICNTSR3` `0x2872` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DMIUEVIDR` `0x4084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`EngVerId` `RO 0xB92A000B`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EngVerId` `RO 0xB92A000B`
`DMIUSMCIFR` `0x4088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`nWP` `RO 0x0`				`WP` `RO 0x0`	`SP` `RO 0x0`	`NumWay` `RO 0xF`						`NumSet` `RO 0x1F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NumSet` `RO 0x1F`
`DMIUINFOR` `0x4092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`									`AE` `RO 0x1`	`SMC` `RO 0x1`	`UST` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UT` `RO 0x9`				`ImplVer` `RO 0x323`