DMIUSMCMLR0

         DMIU System Memory Cache Maintenance Location Register 0


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_DMI0`	`0x1C007000`	`0x1C007348`

Size: 32

Offset: 0x348

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`MntWord` `RW 0x0`						`MntWay` `RW 0x0`						`MntSet` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`MntSet` `RW 0x0`

DMIUSMCMLR0 Fields

Bit Name Description Access Reset

31:26

Bit	Name	Description	Access	Reset
31:26	`MntWord`	This field indicates the data word on which the maintenance operation is to be performed.	`RW`	`0x0`
25:20	`MntWay`	This field indicates the way on which the maintenance operation is to be performed.	`RW`	`0x0`
19:0	`MntSet`	The field indicates the set on which the maintenance operation is to be performed	`RW`	`0x0`

MntWord

This field indicates the data word on which the maintenance operation is to be performed.

RW

0x0

25:20

MntWay

This field indicates the way on which the maintenance operation is to be performed.

RW

0x0

19:0

MntSet

The field indicates the set on which the maintenance operation is to be performed

RW

0x0