DMIUSMCIFR
DMIU System Memory Cache Information Register
| Module Instance | Base Address | Register Address |
|---|---|---|
i_ccu__DSU__1c000000__CCU_DMI0
|
0x1C007000
|
0x1C007FF8
|
Size: 32
Offset: 0xFF8
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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DMIUSMCIFR Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:28 |
nWP
|
Number of way partitioning register pair minus one |
RO
|
0x0
|
| 27 |
WP
|
Way Partitioning support exist |
RO
|
0x0
|
| 26 |
SP
|
This field indicates if scratch pad feature is eanbled when set |
RO
|
0x0
|
| 25:20 |
NumWay
|
This field indicates the number of ways(i.e. the associativity) minus one in the system memory cache |
RO
|
0xF
|
| 19:0 |
NumSet
|
This field indicates the number of sets in the system memory cache minus one in this DMIU. To determine the total number of sets in the system memory cache, this value must be multiplied by the number of DMIUs that implement the system memory cache |
RO
|
0x1F
|