DMIUSMCMAR
DMIU System Memory Cache Maintenance Activity Register
| Module Instance | Base Address | Register Address |
|---|---|---|
i_ccu__DSU__1c000000__CCU_DMI0
|
0x1C007000
|
0x1C007344
|
Size: 32
Offset: 0x344
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
|
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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DMIUSMCMAR Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:1 |
Rsvd1
|
Reserved |
RO
|
0x0
|
| 0 |
MntOpActv
|
This bit is set when any cache maintenance operation is in progress and is clear otherwise |
RO
|
0x0
|