DMIUSMCTCR

         DMIU System Memory Cache Transaction Control Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_DMI0`	`0x1C007000`	`0x1C007300`

Size: 32

Offset: 0x300

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd1` `RO 0x0`														`AllocEn` `RW 0x0`	`LookupEn` `RW 0x0`

DMIUSMCTCR Fields


Bit	Name	Description	Access	Reset
31:2	`Rsvd1`	Reserved	`RO`	`0x0`
1	`AllocEn`	This bit enables allocation into system memory cache.	`RW`	`0x0`
0	`LookupEn`	This bit enables system memory cache.	`RW`	`0x0`