DMIUINFOR 

         DMIU Information Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__CCU_DMI0 0x1C007000 0x1C007FFC

Size: 32

Offset: 0xFFC

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Valid

RO 0x1

Rsvd1

RO 0x0

AE

RO 0x1

SMC

RO 0x1

UST

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UT

RO 0x9

ImplVer

RO 0x323

DMIUINFOR Fields

Bit Name Description Access Reset
31 Valid 
Implemented
 RO 0x1
30:22 Rsvd1 
Reserved
 RO 0x0
21 AE 
Atomic Engine Present
 RO 0x1
20 SMC 
System Memory Cache Present
 RO 0x1
19:16 UST 
Unit sub Type: specifies the Ncore unit native interface type
            0x0 - AXI
            0x1 - ACE-Lite
            0x2 - ACE-Lite E
            0x3 - ACE 
            0x4 - 0x7 - Reserved 
            0x8 - CHI-A
            0x9 - CHI-B
            0xA - 0xF - Reserved
 RO 0x0
15:12 UT 
Unit Type: specifies the Ncore unit type
            0x0 - CAIU
            0x1 - NCAIU
            0x2 - NCAIU with proxy cache
            0x3 - 0x7 - Reserved
            0x8 - DCE
            0x9 - DMI
            0xA - DII
            0xB - DVE 
            0xC - 0xF - Reserved
 RO 0x9
11:0 ImplVer 
Implementation Version
 RO 0x323