DMIUSMCMLR1

         DMIU System Memory Cache Maintenance Location Register 1


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_DMI0`	`0x1C007000`	`0x1C00734C`

Size: 32

Offset: 0x34C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`MntRange` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`MntAddr` `RW 0x0`

DMIUSMCMLR1 Fields

Bit Name Description Access Reset

31:16

Bit	Name	Description	Access	Reset
31:16	`MntRange`	This field indicates the range for flush operations in number of cache lines. This field is used when doing flushes based on address or set/way range.	`RW`	`0x0`
15:0	`MntAddr`	This field contains the high-order address bits of the address on which the maintenance operation is to be performed	`RW`	`0x0`

MntRange

This field indicates the range for flush operations in number of cache lines.
            This field is used when doing flushes based on address or set/way range.

RW

0x0

15:0

MntAddr

This field contains the high-order address bits of the address on which the maintenance operation is to be performed

RW

0x0