High-Performance Memory Controller II SDRAM Intel® FPGA IP Core

The High-Performance Memory Controller II SDRAM Intel FPGA IP core handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM at speeds up to 933 MHz. The intellectual property (IP) core initializes the memory devices, manages SDRAM banks, translates read-and-write requests from the local interface into all the necessary SDRAM command signals, and performs command and data reordering.

High-Performance Memory Controller II SDRAM Intel® FPGA IP Core

The High-Performance Memory Controller II SDRAM Intel FPGA IP core is a drop-in replacement for the existing SDRAM controller with the following new enhanced features:

  • Quarter-rate controller
  • 2-T command timing to maintain command channel bandwidth
  • 50 percent higher random access efficiency with command and data reordering
  • Power-down and self-refresh support
  • Error correction code (ECC) with sub-word writes
  • This IP is included in the IP base suite which is bundled with Intel® Quartus® Prime Standard and Pro Edition Software.

Features

  • Support for industry-standard DDR, DDR2, and DDR3 SDRAM devices and modules
  • Includes support for registered DIMMs
  • Supports efficient bank interleaving
  • Look-ahead bank management
  • Issue activate and precharge commands early
  • Use auto-precharge when possible
  • In-order read/writes (no reordering)
  • Bank management architecture, which minimizes latency
  • Read/write accesses with auto-precharge
  • Automatic cancellation of auto-precharge on page hits
  • Avalon Memory Mapped interface
  • Adapter for native interface
  • Avalon agent interface for access to CSR
  • Burst size adaptation for efficient DRAM accesses
  • Built-in burst adapter
  • Combines short local transactions into memory bursts
  • Split long local transactions into memory bursts
  • Integrated low-latency quarter-rate, half-rate, and full-rate system interface
  • Support an optional half-system interface speed
  • Maintain the controller in the faster clock domain to reduce latency
  • Flexible, robust design
  • 1, 2, 4, or 8 chip-select signals
  • Configurable data width including DQ strobe (DQS) read postamble control logic and optional non-DQS read mode for side banks (Intel Stratix® FPGA series)
  • Automatic or user-controlled refresh
  • Data mask signals for partial write operations
  • Quick and easy implementation
  • IP Toolbench-generated constraint script
  • Top-level example design shipped as a deliverable with the Intel FPGA IP function
  • IP functional simulation models used in Intel FPGA supported VHDL and Verilog HDL simulators
  • Available in clear-text for use with custom controller
  • Integrated command and data reordering to allow for improved memory bandwidth efficiency
  • Power down and self-refresh support
  • Well documented clear text RTL for ease of use
  • Platform Designer (formerly Qsys) compliant to enable system-level design
  • Supports up to 933 MHz memory speed at quarter-rate (233 MHz controller clock)
  • Five-cycle controller latency

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