50G Ethernet Intel® FPGA IP

The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50 Gbps Ethernet IP core is a 128-bit Avalon® streaming interface (Avalon-ST). It maps to two 25.78125 Gbps transceivers.

Read the 50 Gbps ethernet IP core user guide ›

Read the Low Latency 50G Ethernet Intel® FPGA IP user guide ›

Read the Low Latency 50G Ethernet Intel® FPGA IP Design Example user guide ›

Read the F-Tile Low Latency 50G Ethernet Intel® FPGA IP user guide ›

Read the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example user guide ›

50G Ethernet Intel® FPGA IP

The IP core provides standard media access control (MAC) and physical coding sublayer (PCS), and PMA functions shown in the following block diagram. The PHY comprises the PCS and PMA.

Features

PHY:

  • Soft PCS logic that interfaces seamlessly to Intel® Agilex® F-Tile FPGA 51.5625 gigabits per second (Gbps) serial transceiver.

Frame structure control:

  • Support for jumbo packets, defined as packets greater than 1,500 bytes.
  • Receive (RX) cyclic redundancy check (CRC) removal and pass-through control. Transmit (TX) CRC generation.
  • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.

Frame monitoring and statistics:

  • RX CRC checking and error reporting.
  • Optional RX strict SFD checking per IEEE specification.
  • RX malformed packet checking per IEEE specification.
  • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.

Debug and testability:

  • Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
  • Optional access to Intel® FPGA Debug Host Endpoint (ADME) for serial link debugging or monitoring PHY signal integrity.

User system interfaces:

  • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
  • Avalon® streaming (Avalon-ST) data path interface connects to client logic.
  • Ready latency of 0 clock cycles for Avalon-ST TX interface.
  • Hardware and software reset control.

IP Status

 

Status

Production

Ordering Codes

50G MAC/PHY

IP-50GEUMACPHY
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