Intel® Simics® Simulator for Altera® FPGAs: Release Notes
5.9.3. Known Issues
Issue |
Workaround |
|---|---|
First SPI transaction issued from other than core 0 may fail in the Agilex™ 5 E-Series Universal Virtual Platform when multicore is enabled. The problem is related to synchronization between SPI timed events generated by core[0] and the clock in the core that generates the SPI transaction. |
Reduce the CPU switch time (quantum time):set-time-quantum 80 Note: This affects the simulation performance. Fixed in 23.4 release. |
In the Agilex™ 5 E-Series Universal Virtual Platform, it has been identified that booting from QSPI with a JFFS2 format image is taking considerably longer time when compared with booting from SDCard, NAND flash, or QSPI with UBIFS format. |
Use QSPI image with UBIFS format. Fixed in 23.4 release. |
There is a mismatch between the real CPU's clock frequency being used in the simulation and the one reported by the target software when the clock frequency is read from the clock manager registers. |
Since the clock manager is not being used to set the CPU's clock frequency, ignore this information printed by the target software. |
In the Agilex™ 5 E-Series Universal Virtual Platform, NAND data image might be larger than 128 MB affecting the boot from NAND flow |
Limit the size of the NAND flash data image to 128 MB. You can achieve this by reducing the footprint of the root file system using the minimal image version. Fixed in 23.4 release. |
Linux TFTP operations fail with timeout with large files. |
Transfer files smaller than 20 MB with TFTP. For larger file sizes, use SCP or copy the file directly into the file system in any of the available flash devices. Fixed in 23.4 release. |
Linux kernel panic and data corruption are observed on transmitting TCP/UDP packets over a VLAN interface after the HPS Simics model fails to update the header of Rx writeback descriptor. |
Fixed in 23.4 release. |
Linux kernel reports CPU stalling on reception of TCP/UDP packets transferred at high bit rates since the HPS Simics model fails to handle interrupts that are getting triggered faster than this can process them. |
Reduce the transfer bit rate in the packet transmitter side. Tested to work on transfer rates below or equal to 50 Mbps. |
The Ashling* RiscFree* IDE for Intel FPGA fails to recognize target scripts different than .simics extension files making the simulation fails to be launched. |
Prevent facing this problem keeping consistency with Intel Simics script nomenclature by renaming the target script to have a .simics extension. |
The Ashling* RiscFree* IDE for Intel FPGA fails to launch a simulation when too much information is being printed in Intel Simics CLI. |
Suppress the Intel Simics console to print to a minimum. |
The simulation may fail with the following signature due to the definition of the LD_LIBRARY_PATH environment variable: Segmentation fault (SIGSEGV) in main thread #0 0x0000000000002280 The simulation state has been corrupted. Simulation cannot continue. Please restart Simics. There is no frontend to return control to. Simics will exit. |
The definition of the LD_LIBRARY_PATH environment variable defined with Intel Quartus Prime software may create conflicts with the libraries that the Simics Simulator for Intel FPGAs uses. The workaround for this issue is to remove the environment variable. |
By default USB3 HS disk (usb3_hs_disk) is not connected because there is a single port (usb1_typec) for both USB3 disks. |
If USB3 HS disks want to be used, it's necessary to unplug the USB3 disk (usb3_disk) first to release the usb1_typec port. Fixed in 23.4 release. |