Intel® Simics® Simulator for Altera® FPGAs: Release Notes

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ID 870556
Date 12/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Intel® Simics® Simulator for Altera® FPGAs 3. Supported Devices and Virtual Platforms 4. Release Strategy 5. Release Notes 6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes
5. Release Notes x
5.1. Release Notes for Version 25.3 5.2. Release Notes for Version 25.1.1 5.3. Release Notes for Version 25.1 5.4. Release Notes for Version 24.3.1 5.5. Release Notes for Version 24.3 5.6. Release Notes for Version 24.2 5.7. Release Notes for Version 24.1 5.8. Release Notes for Version 23.4 5.9. Release Notes for Version 23.3
5.1. Release Notes for Version 25.3 x
5.1.1. New Features 5.1.2. Features Released and Issues Fixed 5.1.3. Known Issues
5.2. Release Notes for Version 25.1.1 x
5.2.1. New Features 5.2.2. Features Released and Issues Fixed 5.2.3. Known Issues
5.3. Release Notes for Version 25.1 x
5.3.1. New Features 5.3.2. Features Released and Issues Fixed 5.3.3. Known Issues
5.4. Release Notes for Version 24.3.1 x
5.4.1. New Features 5.4.2. Features Released and Issues Fixed 5.4.3. Known Issues
5.5. Release Notes for Version 24.3 x
5.5.1. New Features 5.5.2. Features Released and Issues Fixed 5.5.3. Known Issues
5.6. Release Notes for Version 24.2 x
5.6.1. New Features 5.6.2. Features Released and Issues Fixed 5.6.3. Known Issues
5.7. Release Notes for Version 24.1 x
5.7.1. New Features 5.7.2. Features Released and Issues Fixed 5.7.3. Known Issues
5.8. Release Notes for Version 23.4 x
5.8.1. New Features 5.8.2. Features Released and Issues Fixed 5.8.3. Known Issues
5.9. Release Notes for Version 23.3 x
5.9.1. New Features 5.9.2. Features Released and Issues Fixed 5.9.3. Known Issues
1. Introduction
2. Intel® Simics® Simulator for Altera® FPGAs
3. Supported Devices and Virtual Platforms
4. Release Strategy
5. Release Notes
6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes

5.8.2. Features Released and Issues Fixed

Table 30.  Features Released and Issues Fixed in Version 23.4

Feature Description

Intel Simics Device Affected

Component

Feature: Implementation of FPGA-to-HPS bridges that allow to perform transactions from the FPGA logic to access the HPS or SDRAM. This is documented in Agilex™ 5 Virtual Platform Simics User Guide.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Feature: NAND model to use same NAND Flash used in SM Devkit. Changed the NAND device to match the model used in dev kit(MT29F32G08ABCABH).

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: Unable to boot past uboot SPL with the SM A0 resource. Fixed an issue that causes that SPL get hung. Implemented ready signal in ecc_intstatus_serr 0x10D1 209C and ecc_intstatus_derr 0x10D1 20A0. Therefore, U-Boot will poll those registers before accessing MPFE CSR registers.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: Rx_Multicast_Packets_Good_Low MMC register not cleared on. MMC registers are expected to be cleared on reading. For multicast packet count, Tx_Multicast_Packets_Good_Low value getting reset after every read, but Rx_Multicast_Packets_Good_Low value retains even after reading.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: Running iperf3 on VLAN interface causing kernel panic. In a multi-board configuration implemented iperf3 operations to send packets from one board to the other using iperf3 a kernel panic is being observed. The root cause identified is that transmitting any TCP/UDP packets over VLAN interface causes kernel panic/data corruption. This is because, during the split header, Simics is not updating the header length in the Rx writeback descriptor correctly

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: Only First SPI transaction fails on Zephyr CLI application.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: Linux boot from QSPI is sluggish on SIMICS. Observed very long Linux boot time approximately 1 hour when booting Linux from QSPI. Observed that CPU is waiting in IDLE state for long periods of time. Removing a HW patch applied for N5X.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: NAND write and read data doesn't match when ECC is disabled. When ECC is disabled for NAND Linux driver, write data and read data doesn't match on SIMICS. This has been fixed in Linux NAND driver.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: I2C read/write operation fail on I3C bus. The transaction fails showing the following message: [system.board.fpga.soc_inst.hps_subsys.agilex_hps.i3c0 info] host_state_machine.transfer_machine.i2c_priv_write.fifo underflow! after writing into COMMAND_QUEUE_PORT . It was found that the Simics I3C VP model private I2C transfers are implemented in such a way that pushing data to TX FIFO transfer is always expected to be accompanied by a Command Data Structure, which is not happening.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: Linux PTP App showing error message Received SYNC without timestamps. When upgrading the linuxptp app (ptp4l) from version 3.1.1 to version 4.1, there is an error message printout saying that Received SYNC without timestamps. After debugging, it was found that the update of the PTP Version header can cause this issue.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: The USB disks are connected only if the corresponding image is specified.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform
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