Intel® Simics® Simulator for Altera® FPGAs: Release Notes

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ID 870556
Date 12/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Intel® Simics® Simulator for Altera® FPGAs 3. Supported Devices and Virtual Platforms 4. Release Strategy 5. Release Notes 6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes
5. Release Notes x
5.1. Release Notes for Version 25.3 5.2. Release Notes for Version 25.1.1 5.3. Release Notes for Version 25.1 5.4. Release Notes for Version 24.3.1 5.5. Release Notes for Version 24.3 5.6. Release Notes for Version 24.2 5.7. Release Notes for Version 24.1 5.8. Release Notes for Version 23.4 5.9. Release Notes for Version 23.3
5.1. Release Notes for Version 25.3 x
5.1.1. New Features 5.1.2. Features Released and Issues Fixed 5.1.3. Known Issues
5.2. Release Notes for Version 25.1.1 x
5.2.1. New Features 5.2.2. Features Released and Issues Fixed 5.2.3. Known Issues
5.3. Release Notes for Version 25.1 x
5.3.1. New Features 5.3.2. Features Released and Issues Fixed 5.3.3. Known Issues
5.4. Release Notes for Version 24.3.1 x
5.4.1. New Features 5.4.2. Features Released and Issues Fixed 5.4.3. Known Issues
5.5. Release Notes for Version 24.3 x
5.5.1. New Features 5.5.2. Features Released and Issues Fixed 5.5.3. Known Issues
5.6. Release Notes for Version 24.2 x
5.6.1. New Features 5.6.2. Features Released and Issues Fixed 5.6.3. Known Issues
5.7. Release Notes for Version 24.1 x
5.7.1. New Features 5.7.2. Features Released and Issues Fixed 5.7.3. Known Issues
5.8. Release Notes for Version 23.4 x
5.8.1. New Features 5.8.2. Features Released and Issues Fixed 5.8.3. Known Issues
5.9. Release Notes for Version 23.3 x
5.9.1. New Features 5.9.2. Features Released and Issues Fixed 5.9.3. Known Issues
1. Introduction
2. Intel® Simics® Simulator for Altera® FPGAs
3. Supported Devices and Virtual Platforms
4. Release Strategy
5. Release Notes
6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes

5.7.2. Features Released and Issues Fixed

Table 26.  Features Released and Issues Fixed in Version 24.1

Feature Description

Intel Simics Device Affected

Component

Feature: PHY address changed from 1 to 0 to enable the eSW eth support for AIC0 and OOBE2 daughter cards.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Feature: GMAC interface updated to match OOB Daughter card (ETH2 interface used now in VP instead of ETh0).

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fix: Fix TSN MMC and IPC counter thresholds.

Agilex™ 5 E-Series

Agilex™ 5 E-Series HPS

Fix: USB disk not visible when $usb3_hs_image_filename is configured. To solve this problem now USB disks are instantiated in VP only if a disk image is provided in the target script.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fix: Remove usb0_otg port/slot options for usb3_disk on auto-tab completion in simics CLI.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Feature: Support of pre-loading of handoff data in OCRAM to emulate SDM handoff loading.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Feature: Add support to OCRAM firewall registers so U-Boot Linux can access OCRAM region with SMMU translation table.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Feature: Increase the size of DDR memory from 4 GB to 8 GB. Also request/response from IO96B controller indicates 8GB now.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform Agilex™ 5 E-Series EMIF mailbox

Fix: B0 feature. WFE signal connection to timer was overridden by the connection to sysmgr. This was causing TSN PTP and USB failures.

Agilex™ 5 E-Series

Agilex™ 5 E-Series HPS

Fix: B0 feature. Update register definition to match B0 device.

Agilex™ 5 E-Series

Agilex™ 5 E-Series HPS

Feature: Set A0 as the default stepping for the Agilex™ 5 E-Series model until B0 silicon is available.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform Agilex™ 5 E-Series HPS

Feature: Added input reset signal support to PIO devices in FPGA fabric design model.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform FPGA Fabric model (Peripheral sub-system)

Fixed: DDR_ECC_DBE_STATUS bit is not updated to 1 in BOOT_SCRATCH_REG 3 by SDM when an DBE is injected. DBE injection should be followed by an SBE injection.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Fixed: Hang observed in Simics simulation when calling flushcache() function from a 32 bit Linux User mode application.

Agilex™ 5 E-Series

Agilex™ 5 E-Series HPS (MPU)
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