Intel® Simics® Simulator for Altera® FPGAs: Release Notes

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ID 870556
Date 12/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Intel® Simics® Simulator for Altera® FPGAs 3. Supported Devices and Virtual Platforms 4. Release Strategy 5. Release Notes 6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes
5. Release Notes x
5.1. Release Notes for Version 25.3 5.2. Release Notes for Version 25.1.1 5.3. Release Notes for Version 25.1 5.4. Release Notes for Version 24.3.1 5.5. Release Notes for Version 24.3 5.6. Release Notes for Version 24.2 5.7. Release Notes for Version 24.1 5.8. Release Notes for Version 23.4 5.9. Release Notes for Version 23.3
5.1. Release Notes for Version 25.3 x
5.1.1. New Features 5.1.2. Features Released and Issues Fixed 5.1.3. Known Issues
5.2. Release Notes for Version 25.1.1 x
5.2.1. New Features 5.2.2. Features Released and Issues Fixed 5.2.3. Known Issues
5.3. Release Notes for Version 25.1 x
5.3.1. New Features 5.3.2. Features Released and Issues Fixed 5.3.3. Known Issues
5.4. Release Notes for Version 24.3.1 x
5.4.1. New Features 5.4.2. Features Released and Issues Fixed 5.4.3. Known Issues
5.5. Release Notes for Version 24.3 x
5.5.1. New Features 5.5.2. Features Released and Issues Fixed 5.5.3. Known Issues
5.6. Release Notes for Version 24.2 x
5.6.1. New Features 5.6.2. Features Released and Issues Fixed 5.6.3. Known Issues
5.7. Release Notes for Version 24.1 x
5.7.1. New Features 5.7.2. Features Released and Issues Fixed 5.7.3. Known Issues
5.8. Release Notes for Version 23.4 x
5.8.1. New Features 5.8.2. Features Released and Issues Fixed 5.8.3. Known Issues
5.9. Release Notes for Version 23.3 x
5.9.1. New Features 5.9.2. Features Released and Issues Fixed 5.9.3. Known Issues
1. Introduction
2. Intel® Simics® Simulator for Altera® FPGAs
3. Supported Devices and Virtual Platforms
4. Release Strategy
5. Release Notes
6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes

5.9.2. Features Released and Issues Fixed

Table 34.  Features Released and Issues Fixed in Version 23.3

Feature Description

Intel Simics Device Affected

Component

Booting Linux and Zephyr from QSPI and NAND devices. New parameters added to the target script for this.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Hierarchy in Agilex™ 5 E-Series Universal virtual platform updated to match GHRD. FPGA Example design updated to create peripheral sub-component.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

I2C EEPROM devices connected to I3C0 and I3C1 controllers.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

SDcard size in the virtual platform increased from 4 GB to 16 GB.

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform

Warm reset triggered after WDT expiration.

Agilex™ 5 E-Series

Agilex™ 5 E-Series HPS model

I3C Controller can be configured as a target device.

Agilex™ 5 E-Series

Agilex™ 5 E-Series HPS Model

Core frequency set through target script parameter instead of Clock Manager settings. Default CPU clock frequency is 400 MHz.

Agilex™ 5 E-Series

Agilex™ 5 E-Series HPS model

Model adapted to match simulation time with time in OS in the target system

Agilex™ 5 E-Series HPS model

Support TFTP operations in U-Boot.

Agilex™ 5 E-Series

U-Boot Target software

TFTP operation in Linux does not require ethtool workaround.

Agilex™ 5 E-Series

Linux Target software

Ethernet PHY port address updated to match GHRD

Agilex™ 5 E-Series

Agilex™ 5 E-Series Universal Virtual Platform Linux Target software

Zephyr supports I3C, SPI as master, and NAND

Agilex™ 5 E-Series

Zephyr Target software

Fixed a problem in the Ashling* RiscFree* IDE where the simulation failed frequently when launched from the Project Explorer window.

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Ashling* RiscFree* IDE for Intel FPGAs

Fixed a problem in the Ashling* RiscFree* IDE where much information was not being received about an error condition identified in the target script or during the process of launching the simulation.

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Ashling* RiscFree* IDE for Intel FPGAs
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