Intel® Simics® Simulator for Altera® FPGAs: Release Notes

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ID 870556
Date 12/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Intel® Simics® Simulator for Altera® FPGAs 3. Supported Devices and Virtual Platforms 4. Release Strategy 5. Release Notes 6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes
5. Release Notes x
5.1. Release Notes for Version 25.3 5.2. Release Notes for Version 25.1.1 5.3. Release Notes for Version 25.1 5.4. Release Notes for Version 24.3.1 5.5. Release Notes for Version 24.3 5.6. Release Notes for Version 24.2 5.7. Release Notes for Version 24.1 5.8. Release Notes for Version 23.4 5.9. Release Notes for Version 23.3
5.1. Release Notes for Version 25.3 x
5.1.1. New Features 5.1.2. Features Released and Issues Fixed 5.1.3. Known Issues
5.2. Release Notes for Version 25.1.1 x
5.2.1. New Features 5.2.2. Features Released and Issues Fixed 5.2.3. Known Issues
5.3. Release Notes for Version 25.1 x
5.3.1. New Features 5.3.2. Features Released and Issues Fixed 5.3.3. Known Issues
5.4. Release Notes for Version 24.3.1 x
5.4.1. New Features 5.4.2. Features Released and Issues Fixed 5.4.3. Known Issues
5.5. Release Notes for Version 24.3 x
5.5.1. New Features 5.5.2. Features Released and Issues Fixed 5.5.3. Known Issues
5.6. Release Notes for Version 24.2 x
5.6.1. New Features 5.6.2. Features Released and Issues Fixed 5.6.3. Known Issues
5.7. Release Notes for Version 24.1 x
5.7.1. New Features 5.7.2. Features Released and Issues Fixed 5.7.3. Known Issues
5.8. Release Notes for Version 23.4 x
5.8.1. New Features 5.8.2. Features Released and Issues Fixed 5.8.3. Known Issues
5.9. Release Notes for Version 23.3 x
5.9.1. New Features 5.9.2. Features Released and Issues Fixed 5.9.3. Known Issues
1. Introduction
2. Intel® Simics® Simulator for Altera® FPGAs
3. Supported Devices and Virtual Platforms
4. Release Strategy
5. Release Notes
6. Document Revision History for Intel® Simics® Simulator for Altera® FPGAs Release Notes

5.4.2. Features Released and Issues Fixed

Table 14.  Features Released and Issues Fixed in Version 24.3.1

Feature Description

Intel Simics Device Affected

Component

GIC registers are unknown to the ARM 32-bit instructions, so these instructions fail to execute when accessing these registers.

Agilex 5

Agilex™ 5 HPS

Memory read/write access at byte-by-byte level throws memory region not mapped error.

Agilex 5

Agilex™ 5 HPS
Level Two Title