Agilex™ 5 FPGA E-Series 013B Development Kit User Guide

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ID 860700
Date 10/16/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 013B Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 5 FPGA E-Series 013B Development Kit (DK-A5E013BM16AEA) 3.4.2. Restoring SD Card with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 5 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 5 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 013B Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.3.6. HPS I/O48 Interface

For the Agilex™ 5 FPGA E-Series 013B Development Kit (DK-A5E013BM16AEA) versions, the HPS components are depopulated from the board. The HPS components include: USB2.0 DRP (Dual Role Port), 2-wire UART, 10/100/1000 Ethernet, Micro-SD card, I2C, and JTAG accessibility.
Table 27.  HPS Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
HPS_GPIO0 B29 1.8 V HPS LED0
HPS_GPIO1 A27 1.8 V Ethernet interrupt
HPS_GPIO2 C27 1.8 V UART transmit
HPS_GPIO3 F24 1.8 V UART receive
HPS_GPIO4 B28 1.8 V I2C data
HPS_GPIO5 F23 1.8 V I2C clock
HPS_GPIO6 D27 1.8 V Ethernet MDIO
HPS_GPIO7 E22 1.8 V Ethernet MDC
HPS_GPIO8 C26 1.8 V I3C data
HPS_GPIO9 D22 1.8 V I3C clock
HPS_GPIO10 A23 1.8 V HPS 25 MHz clock
HPS_GPIO11 A26 1.8 V HPS LED1
HPS_GPIO12 D25 1.8 V USB2.0 clock
HPS_GPIO13 B26 1.8 V USB2.0 STP
HPS_GPIO14 B25 1.8 V USB2.0 DIR
HPS_GPIO15 E17 1.8 V USB2.0 DATA 0
HPS_GPIO16 A16 1.8 V USB2.0 DATA 1
HPS_GPIO17 E16 1.8 V USB2.0 NXT
HPS_GPIO18 D24 1.8 V USB2.0 DATA 2
HPS_GPIO19 E21 1.8 V USB2.0 DATA 3
HPS_GPIO20 B23 1.8 V USB2.0 DATA 4
HPS_GPIO21 D20 1.8 V USB2.0 DATA 5
HPS_GPIO22 B24 1.8 V USB2.0 DATA 6
HPS_GPIO23 A24 1.8 V USB2.0 DATA 7
HPS_GPIO24 D23 1.8 V SD card data 0
HPS_GPIO25 C25 1.8 V SD card data 1
HPS_GPIO26 A18 1.8 V SD card clock
HPS_GPIO27 C20 1.8 V SD card I/O voltage select
HPS_GPIO28 A17 1.8 V HPS push button 0
HPS_GPIO29 C21 1.8 V SD card data 2
HPS_GPIO30 C23 1.8 V SD card data 3
HPS_GPIO31 E20 1.8 V SD card command
HPS_GPIO32 C22 1.8 V HPS JTAG TCK
HPS_GPIO33 D19 1.8 V HPS JTAG TMS
HPS_GPIO34 B21 1.8 V HPS JTAG TDO
HPS_GPIO35 A22 1.8 V HPS JTAG TDI
HPS_GPIO36 B16 1.8 V Ethernet TX clock
HPS_GPIO37 B18 1.8 V Ethernet TX enable
HPS_GPIO38 E19 1.8 V Ethernet RX clock
HPS_GPIO39 B20 1.8 V Ethernet RX data valid
HPS_GPIO40 C18 1.8 V Ethernet TX data 0
HPS_GPIO41 A21 1.8 V Ethernet TX data 1
HPS_GPIO42 D17 1.8 V Ethernet RX data 0
HPS_GPIO43 A19 1.8 V Ethernet RX data 1
HPS_GPIO44 D18 1.8 V Ethernet TX data 2
HPS_GPIO45 B19 1.8 V Ethernet TX data 3
HPS_GPIO46 C17 1.8 V Ethernet RX data 2
HPS_GPIO47 C16 1.8 V Ethernet Rx data 3
Level Two Title