Agilex™ 5 FPGA E-Series 013B Development Kit User Guide

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ID 860700
Date 9/02/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 013B Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the USB-Blaster III Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board 3.3. Modes of Operations 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 5 FPGA E-Series 013B Development Kit (DK-A5E013BM16AEA) 3.4.2. Restoring Board QSPI Flash U51 with Default Factory Image on Agilex™ 5 FPGA E-Series 013B Development Kit (DK-A5E013BM16AES1) 3.4.3. Restoring SD Card with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. BTS Functionalities
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Agilex™ 5 FPGA Functionality 4.2.2. Other Functionalities
4.2.1. The Agilex™ 5 FPGA Functionality x
4.2.1.1. The Configure Menu 4.2.1.2. The GPIO Tab 4.2.1.3. The Memory Tab 4.2.1.4. The Transceiver Tab
4.2.1.2. The GPIO Tab x
4.2.1.2.1. The LED Tab 4.2.1.2.2. The Push Button Tab
4.2.1.3. The Memory Tab x
4.2.1.3.1. The Fabric COMP Tab 4.2.1.3.2. The HPS COMP Tab
4.2.1.4. The Transceiver Tab x
4.2.1.4.1. The DP Tab
4.2.2. Other Functionalities x
4.2.2.1. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview and Components A.2. Input and Output Components A.3. Components and Interfaces A.4. Clock Circuits A.5. System Power A.6. Power Guidelines A.7. Power Distribution System A.8. Expansion Boards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
A.2. Input and Output Components x
A.2.1. Push Buttons A.2.2. Switches A.2.3. LEDs
A.3. Components and Interfaces x
A.3.1. PCI Express* ( PCIe* ) Interface A.3.2. DisplayPort Interface A.3.3. MIPI Interface A.3.4. LPDDR4 Interfaces A.3.5. Raspberry Pi* , Pmod, and PCIe* x1 Interfaces A.3.6. HPS I/O48 Interface A.3.7. I2C
A.6. Power Guidelines x
A.6.1. Primary Mode—As a Standalone Evaluation Board A.6.2. Optional Mode—As a PCIe* Add-in Card in PCIe* Host System
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 013B Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.4. Clock Circuits

Figure 27.  Agilex™ 5 FPGA E-Series 013B Development Kit Clocks and Default Frequencies
Table 30.  Onboard Oscillators Sources for the FPGA
Source Schematic Signal Name

Frequency

(MHz)

 I/O Standard

Agilex™ 5 Pin Number

(P/N)		 Application
U23 HVIO_PLLREFCLK 100 3.3V LVCMOS AJ27 HVIO PLL reference clock
LP4_2A_REFCLK_P/N 166.67 LVDS AF3/AE4 LPDDR4 bank 2A reference clock
LP4_3A_REFCLK_P/N 166.67 LVDS A7/B6 LPDDR4 bank 3A reference clock
PTP_3A_REFCLK 250 1.1V LVCMOS E2 PTP bank 3A reference clock
FPGA_FABRIC_TOD_CLK 125 1.1V LVCMOS N1 TOD bank 2A reference clock
PPS_2A_REFCLK 10 1.1V LVCMOS N2 PPS bank 2A reference clock
MIPI_2A_REFCLK_P/N 150 LVDS AC6/AC5 MIPI bank 2A reference clock
MIPI_3A_REFCLK_P/N 150 LVDS F2/E1 MIPI bank 3A reference clock
DP_BANK1A_REFCLK_P/N 150 LVDS P25/P24 DisplayPort bank 1A reference clock
RPI_PCIE_REFCLK_P/N 100 HCSL J14.4/J14.5 PCIe* root port reference clock
PCIE_EP_REFCLK_P/N 100 HCSL M24/M25 PCIe* bank 1A endpoint clock
Y5 SDM_CONFIG_CLK 100 1.8V LVCMOS AG11 FPGA configuration clock
Y1 HPS_OSC_CLK 25 1.8V LVCMOS A23 HPS system clock
Level Two Title