Agilex™ 5 FPGA E-Series 013B Development Kit User Guide

ID 860700
Date 9/02/2025
Public
Document Table of Contents

6.1. Golden Top

You can use the Golden Top project as the starting point for your designs. It comes loaded with constraints, pin locations, define I/O standard, direction and general termination.
  1. Define a macro to enable or disable the corresponding interface in the top-level design entity, and the interfaces that require IP connection are disabled by default.
  2. Open the macro according to the requirements. If the pins are not connected to the IP, a fitter error occurs.