Agilex™ 3 Known Issue List

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ID 855394
Date 11/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Known Issue List for Agilex™ 3 Devices 3. Document Revision History for the Agilex™ 3 Known Issue List
2. Known Issue List for Agilex™ 3 Devices x
2.1. FPGA
2.1. FPGA x
2.1.1. Transceiver 2.1.2. EMIF 2.1.3. HPS
2.1.1. Transceiver x
2.1.1.1. Occasional equalization timeout or PCIe link training failure to achieve expected link speed during speed change, hot reset, and link disable 2.1.1.2. Both ERR_COR and ERR_FATAL messages are sent when TLP with ECRC error is received 2.1.1.3. Multiple error messages are generated by the multifunction device when a non-function-specific error occurs 2.1.1.4. Transmission of all Ethernet frames is suspended upon reception of PAUSE frame request from External link partner 2.1.1.5. Reduced Reference Clock Frequency Options for Certain Output Frequencies in GTS System PLL Clocks IP Description Workaround Status 2.1.1.6. DisplayPort IP Performance Instability Issue 2.1.1.7. IEEE 1588v2 PTP Accuracy Issue for GTS Ethernet Hard IP for 10GE Rate Designs
2.1.2. EMIF x
2.1.2.1. No support for unaligned access to EMIF interfaces using Fabric Direct Access mode or HPS F2SDRAM bridge 2.1.2.2. Lower than expected efficiency for sequential access pattern on fabric EMIF when using secondary memory controller
2.1.3. HPS x
2.1.3.1. The USB 3.1 controller has a spillover condition during IN transfers for bulk endpoint which causes a DBE issue for the ISOC-IN Endpoint 2.1.3.2. USB 3.1 Controller Device Drops eSS ISOC Data if the ITP Delta Value is Greater than 63 units 2.1.3.3. The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition 2.1.3.4. HPS GICv3 ITS unable to access physical memory larger than 32 bits causing MSI-X Interrupt failure 2.1.3.5. SD/eMMC Host Controller Capabilities Register provides incorrect information with regard to 8-bit Embedded Device Support
1. About This Document
2. Known Issue List for Agilex™ 3 Devices
3. Document Revision History for the Agilex™ 3 Known Issue List

2.1.1.5. Reduced Reference Clock Frequency Options for Certain Output Frequencies in GTS System PLL Clocks IP

Description

Some reference clock frequencies listed in the drop-down list are not valid for certain GTS System PLL Clocks IP output frequencies. Selecting an invalid reference clock option will result in incorrect GTS System PLL Clocks IP output frequencies. The invalid reference clock frequency options are available in Quartus® Prime Pro Edition software version 25.3 and earlier. The invalid options will be removed in the future release of the Quartus® Prime Pro Edition software version.

Workaround

There is no workaround. Altera offers a TCL script to verify if the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following alternatives:
  1. Provides a list of alternative reference clock frequencies while maintaining the same output frequency.
  2. Suggests two alternative GTS System PLL Clocks IP output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode.
  3. In some cases, the script suggests retaining the same input and output clock frequencies. This option is possible only if you install the patch for Quartus® Prime Pro Edition version 25.3 or migrate to future versions of Quartus® Prime Pro Edition.
Copy the tcl script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus® Prime Pro Edition project.
  • For Linux operating system, change the directory to the IP folder and execute the command tclsh find_mcnt.tcl.
  • For Windows operating system, run the script from the Tcl Console within the Quartus® Prime Pro Edition Software GUI.
Table 7.  Recommended Actions based on Design Status
Design Status Recommended Actions
Design not impacted Implement the following actions based on your design need:
  • If the design is final and you do not plan to change the System PLL output frequency or reference clock frequency in future versions, you do not need to take any further action.
  • If you want to change the design in the future, either migrate it to a future version of the Quartus® Prime Pro Edition , or install the patch for Quartus® Prime Pro Edition software version 25.3.
Design impacted Implement one of the workarounds suggested in the TCL script. In addition, migrate your design to a future version of the Quartus® Prime Pro Edition software version. If you need to keep your design in Quartus® Prime Pro Edition software version 25.3, install the patch, regenerate the GTS System PLL Clocks IP and recompile your Quartus® Prime project.

Status

Table 8.  Device Status Table
Devices Affected Planned Fix

  • A3Cx100BM16Axxx

  • A3Cx135BM16Axxx

 No planned fix

Refer to the associated Knowledge Base entry to download the TCL script and patch.

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