2.1.2.2. Lower than expected efficiency for sequential access pattern on fabric EMIF when using secondary memory controller
Description
In the following fabric EMIF configurations, you might encounter lower than expected efficiency for sequential access patterns on the secondary memory controller:
- 2chx16 LPDDR4
- 1chx16 of LPDDR4 on the top sub-bank
Workaround
Asynchronous clocking mode (also known as Fabric Direct–User Clock Asynchronous to PHY)
You can improve the efficiency for sequential access pattern on the secondary controller by increasing the AXI clock frequency. Recommendation is to set the AXI clock frequency to 1/4 of memory clock frequency. You can further improve the efficiency of sequential write access pattern on the secondary controller by increasing the burst length as shown in the following table. The data shown in the table is obtained by using a 2ch x16 LPDDR4 design, running at 1066.667 MHz.
| AXI Clock Frequency (MHz) | Pattern | Burst Length | Controller Efficiency (%) | |
|---|---|---|---|---|
| Primary | Secondary | |||
133.333 (Equivalent to Sync Mode) |
Sequential write | 2 | ~90 | ~40 |
| Sequential read | ~90 | ~50 | ||
| 266.667 | Sequential write | 2 | ~90 | ~75 |
| Sequential read | ~90 | ~90 | ||
| Sequential write | 4 | ~90 | ~80 | |
| Sequential read | ~90 | ~90 | ||
| Sequential write | 8 | ~90 | ~90 | |
| Sequential read | ~90 | ~90 | ||
| Sequential write | 16 | ~90 | ~90 | |
| Sequential read | ~90 | ~90 | ||
Random access patterns or mixed traffic patterns can mitigate the differences in the efficiency for the primary controller and secondary controller.
| AXI Clock Frequency (MHz) | Pattern | Burst Length | Controller Efficiency (%) | |
|---|---|---|---|---|
| Primary | Secondary | |||
| 133.333 | Random write | 2 | ~40 | ~39 |
| Random read | ~38 | ~38 | ||
| 266.667 | Random write | 2 | ~41 | ~41 |
| Random read | ~38 | ~38 | ||
With increased AXI clock frequency, the efficiency number reported by the PMON IP represents the utilization of the AXI bus instead of controller efficiency. The following equation represents the efficiency of the memory controller:
Controller efficiency = AXI transactions accepted by AXI bus / Memory Controller Bandwidth * 100 % = ( PMON efficiency * AXI Clock Freq * 256-bit ) / (16-bit * Mem Clock Freq ) * 100%
Synchronous Clocking Mode (also known as Fabric Direct – User Clock Synchronous to PHY)
In LPDDR4 memory interface, when using x16 2-channel configuration for long burst sequential access during write or read operation, performance is limited to 50% per read/write sub-channel for the secondary controller.
If your application requires high controller efficiency for sequential access pattern, you should use asynchronous clocking mode.
Random access patterns or mixed traffic patterns can mitigate the differences in the efficiency for the primary and secondary controllers.
In synchronous clocking mode, the primary controller's efficiency for a x32 LPDDR4 memory interface is reduced because the AXI bus bandwidth is only half that of the memory controller.
AXI Bus Bandwidth = AXI Clock Freq x 256-bit = ( Memory Clock Freq / 8 ) * 256 = 32 * Memory Clock Frequency
Memory Controller Bandwidth = Memory Clock Freq * 2 * 32-bit = 64 * Memory Clock Frequency = 2 * AXI Bus Bandwidth
Status
| Devices Affected | Planned Fix |
|---|---|
|
No planned fix |