Agilex™ 3 Known Issue List

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ID 855394
Date 11/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Known Issue List for Agilex™ 3 Devices 3. Document Revision History for the Agilex™ 3 Known Issue List
2. Known Issue List for Agilex™ 3 Devices x
2.1. FPGA
2.1. FPGA x
2.1.1. Transceiver 2.1.2. EMIF 2.1.3. HPS
2.1.1. Transceiver x
2.1.1.1. Occasional equalization timeout or PCIe link training failure to achieve expected link speed during speed change, hot reset, and link disable 2.1.1.2. Both ERR_COR and ERR_FATAL messages are sent when TLP with ECRC error is received 2.1.1.3. Multiple error messages are generated by the multifunction device when a non-function-specific error occurs 2.1.1.4. Transmission of all Ethernet frames is suspended upon reception of PAUSE frame request from External link partner 2.1.1.5. Reduced Reference Clock Frequency Options for Certain Output Frequencies in GTS System PLL Clocks IP 2.1.1.6. DisplayPort IP Performance Instability Issue 2.1.1.7. IEEE 1588v2 PTP Accuracy Issue for GTS Ethernet Hard IP for 10GE Rate Designs
2.1.2. EMIF x
2.1.2.1. No support for unaligned access to EMIF interfaces using Fabric Direct Access mode or HPS F2SDRAM bridge 2.1.2.2. Lower than expected efficiency for sequential access pattern on fabric EMIF when using secondary memory controller
2.1.3. HPS x
2.1.3.1. The USB 3.1 controller has a spillover condition during IN transfers for bulk endpoint which causes a DBE issue for the ISOC-IN Endpoint 2.1.3.2. USB 3.1 Controller Device Drops eSS ISOC Data if the ITP Delta Value is Greater than 63 units 2.1.3.3. The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition Description Workaround 2.1.3.4. HPS GICv3 ITS unable to access physical memory larger than 32 bits causing MSI-X Interrupt failure 2.1.3.5. SD/eMMC Host Controller Capabilities Register provides incorrect information with regard to 8-bit Embedded Device Support
1. About This Document
2. Known Issue List for Agilex™ 3 Devices
3. Document Revision History for the Agilex™ 3 Known Issue List

2.1.3.3. The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition

Description

There is a possible glitch in the clock output when the power state transitions from U3 to U0. This clock glitch could potentially lock-up flops.

Workaround

No workaround available.

Table 18.  Device Status Table
Devices Affected Planned Fix

  • A3CW100BM16Axxx

  • A3CW135BM16Axxx

 No planned fix
Level Two Title